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Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design Yuan-Hao Chang, Jen-Wei Hsieh, and Tei-Wei Kuo Embedded Systems and Wireless Networking Laboratory Dept. of Computer Science and Information

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Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design

Yuan-Hao Chang, Jen-Wei Hsieh, and Tei-Wei Kuo

Embedded Systems and Wireless Networking Laboratory

  • Dept. of Computer Science and Information Engineering

National Taiwan University Taipei, Taiwan

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2

Outline

  • Introduction
  • System Architecture
  • Motivation
  • An Efficient Static Wear Leveling Mechanism
  • Performance Evaluation
  • Conclusion
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3

Introduction

  • Why Flash Memory
  • Diversified Application Domains

– Portable Storage Devices – Consumer Electronics – Industrial Applications

  • SoC and Hybrid Devices

– Critical System Components

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Introduction

  • Characteristics of Flash Memory

… …

(2KB+64 Byte) (2KB+64 Byte)

… …

(2KB+64 Byte) (2KB+64 Byte)

… …

(2KB+64 Byte) (2KB+64 Byte)

Page: basic write-operation unit.

63

… … 511 … … … … Block: basic erase-operation unit. 64MB SLC Flash Memory

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5 5

System Architecture

*FTL: Flash Translation Layer, MTD: Memory Technology Device

SD, xD,

MemoryStick,

SmartMedia

CompactFlash

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6

Policies – FTL

  • FTL adopts a page-level address translation mechanism.

– Main problem: Large memory space requirement

User data

. . .

Logical Block Address (array index) Physical Block Address (block,page)

Physical Block Address (block,page) Access LBA = 3

Address Translation Table (in main-memory) Flash memory

0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 1,0 1,1 1,2 1,3 (0,3) (0,1) (0,6) (0,4) (4,7) (1,0) (2,1) (1,2) (1,3) 1 2 3 4 5 6 7 8 9 10 11

. . .

Spare data

Spare data LBA=3; ECC=. . .; Status=. . .;

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Policies – NFTL

  • Each logical address under NFTL is divided into a virtual block address

and a block offset.

– e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block

  • ffset = 1011 % 8 = 3

. . .

(9,23)

Write data to LBA=1011

. . .

NFTL

Address Translation Table (in main-memory) Free Free Free Used Free Free Free Free Used Used Used Free Free Free Free Free A Primary Block Address = 9 A Replacement Block Address = 23 VBA=126 Block Offset=3 If the page has been used Write to the first free page

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Outline

  • Introduction
  • System Architecture
  • Motivation

Motivation

  • An Efficient Static Wear Leveling Mechanism
  • Performance Evaluation
  • Conclusion
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Motivation

  • A limited bound on erase cycles

– SLC : 100,000 – MLCx2 : 10,000

  • Applications with frequent access

– Disk cache (e.g., Robson) – Solid State Disks (SSD)

Solid State Disk

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Motivation – Why Static Wear Leveling:

No Wear Leveling

Physical Block Addresses (PBA) Erase Cycles

20 40 60 80 100 1000 2000 3000 4000 5000

Number of Write/Erase Cycles per PBA (75% Static Data)

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Motivation – Why Static Wear Leveling:

Dynamic Wear Leveling

Physical Block Addresses (PBA) Erase Cycles

20 40 60 80 100 1000 2000 3000 4000 5000

Number of Write/Erase Cycles per PBA (75% Static Data)

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Motivation – Why Static Wear Leveling:

Perfect Static Wear Leveling

Physical Block Addresses (PBA) Erase Cycles

20 40 60 80 100 1000 2000 3000 4000 5000

Number of Write/Erase Cycles per PBA (75% Static Data)

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Motivation – Why Static Wear Leveling is So Difficult?

  • An intuitive SWL
  • Problems:

– Block erase – Live-page copying – RAM space – CPU time

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Flash memory counter : free block : dead block : block contains (some) valid data

: index in the selection of a victim block

: index to the selected free block

5 5 4 5 5 4 4 5 4 5 5 4 4 5 5 4

Update data in block 3 Write new data to block 4 GC starts find a victim block

5

Update block 15 GC starts

5 5 5 5

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Motivation – Comparison

Physical Block Addresses (PBA) Erase Cycles

20 40 60 80 100 1000 2000 3000 4000 5000

Perfect SWL

Physical Block Addresses (PBA)

20 40 60 80 100 1000 2000 3000 4000 5000

Intuitive SWL Intuitive SWL

Erase Cycles

20 40 60 80 100 1000 2000 3000 4000 5000

No Wear Leveling

20 40 60 80 100 1000 2000 3000 4000 5000

Dynamic Wear Leveling

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15

Outline

  • Introduction
  • System Architecture
  • Motivation
  • An Efficient Static Wear Leveling Mechanism

An Efficient Static Wear Leveling Mechanism

  • Performance Evaluation
  • Conclusion
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Design Considerations in Static Wear Leveling

  • Scalability Issues

– The limitation on the RAM space – The limitation on computing power

  • Compatibility Issue

– Compatibility with FTL and NFTL

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An Efficient Static Wear Leveling Mechanism

  • A modular design for

compatibility considerations

  • A SWL mechanism

– Block Erasing Table (BET)

  • bit flags

– SW Leveler

  • SWL-Procedure
  • SWL-Update
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The Block Erasing Table (BET)

  • A bit-array: Each bit is for 2k consecutive blocks.

– Small k – in favor of hot-cold data separation – Large k – in favor of small RAM space

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Flash BET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 1 1 1

k=0 k=2

ecnt =0 fcnt =0 ecnt =0 fcnt =0 ecnt =1 fcnt =1 ecnt =2 fcnt =2 ecnt =3 fcnt =2 ecnt =1 fcnt =1 ecnt =2 fcnt =2 ecnt =3 fcnt =2 ecnt =4 fcnt =2 : a block that has been erased in the current resetting interval : an index to a block that the Cleaner wants to erase fcnt : the number of 1’s in the BET ecnt : the total number of block erases done since the BET is reset

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ecnt =1998 fcnt =2

  • An unevenness level (ecnt / fcnt

) >= T  Triggering of the SW Leveler

  • Resetting of BET when all flags are set.

The SW Leveler

0 0 0 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : A block that has been erased in the current resetting interval

1 1 k=2

: An index to a block that the Cleaner wants to erase

fcnt: The number of 1’s in the BET ecnt: the total number of block erases since the BET is erased T: A threshold, T=1000 in this example

: An index in the selection of a block set

ecnt =1999 fcnt =2 ecnt =2000 fcnt =2 2000 / 2 = 1000 >= 1000 (Ecnt / fcnt >= T)

1

: An index that SW Leveler triggers the Cleaner to do garbage collection The Cleaner is triggered to

  • 1. Copy valid data of selected block set to free area,
  • 2. Erase block in the selected block set, and
  • 3. Inform the Allocator to update the address mapping

between LBA and PBA

After a period of time, the total erase count reaches 2998.

ecnt =2004 fcnt =3 ecnt =2998 fcnt =3 ecnt =2999 fcnt =3 ecnt =3000 fcnt =3 3000 / 3 = 1000 >= 1000 (Ecnt / fcnt >= T)

1

ecnt =3004 fcnt =4 After a period of time, the total erase count reaches 3999. ecnt =3999 fcnt =4 ecnt =4000 fcnt =4 4000 / 4 = 1000>=1000 (ecnt / fcnt >=1000) , but all flags in BET are 1 reset BET

Reset to a randomly selected block set (flag)

ecnt =0 fcnt =0

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Main-Memory Requirements

512MB 1GB 2GB 4GB 8GB k=0 256B 512B 1024B 2048B 4096B k=1 128B 256B 512B 1024B 2048B k=2 64B 128B 256B 512B 1024B k=3 32B 64B 128B 256B 512B MLCx2 (1 page = 2 KB, 1 block=128 pages)

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Outline

  • Introduction
  • System Architecture
  • Motivation
  • An Efficient Static Wear Leveling Mechanism
  • Performance Evaluation

Performance Evaluation

  • Conclusion
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Performance Evaluation

  • Metrics

– Endurance Enhancement (First Failure Time) – Additional Overheads (Extra Block Erases)

  • Experiment Setup

– The FTL Layer

  • FTL (Flash Translation Layer protocol)
  • NFTL (NAND Flash Translation Layer protocol)

– Traces:

  • A mobile PC with a 20GB hard disk
  • Duration: One month.
  • Daily activities
  • The average number of Operations: 1.82 writes/sec, 1.97 reads/sec
  • The percentage of accessed LBA’s: 36.62%

– Flash Memory: 1GB MLCx2

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Endurance Improvement

  • The First Failure Time

When k=3 and T=100, the endurance is improved by 100.2%. When k=0 and T=100, the endurance is improved by 87.5%.

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Additional Overhead

  • Extra Block Erases

Extra block erases is less than 3%. Extra block erases is less than 2%.

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Conclusion

  • An Efficient Static Wear Leveling Mechanism

– Small Memory Space Requirement

  • Less than 4KB for 8GB flash memory

– Efficient Implementation

  • An adjustable house-keeping data structure
  • An cyclic queue scanning algorithm
  • Performance Evaluation

– Improvement Ratio of the Endurance:

  • The ratio is more than 50% with proper settings to T and K

– Extra Overhead:

  • It is less than 3% of extra block erase with proper settings
  • There is limited overhead in live-page copyings
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Conclusion

  • Future work

–Endurance and Reliability Problems due to Manufacturing and Capacity Improvements

  • Read/Write Disturbance

Problems

–System Components

  • Memory Hierarchy, Devices,

Adaptors, etc.

–Benchmark Designs

  • Targets on Different Designs

Selected cell IDS Control Gate Drain Source

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~ Thank You ~