Endurance Enhancement of Flash-Memory Storage Systems: An Efficient - PowerPoint PPT Presentation

Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design Yuan-Hao Chang, Jen-Wei Hsieh, and Tei-Wei Kuo Embedded Systems and Wireless Networking Laboratory Dept. of Computer Science and Information Engineering National Taiwan University Taipei, Taiwan

2 Outline • Introduction • System Architecture • Motivation • An Efficient Static Wear Leveling Mechanism • Performance Evaluation • Conclusion

3 Introduction - Why Flash Memory • Diversified Application Domains – Portable Storage Devices – Consumer Electronics – Industrial Applications • SoC and Hybrid Devices – Critical System Components

4 Introduction - Characteristics of Flash Memory … … 0 63 0 … … (2KB+64 Byte) (2KB+64 Byte) Block: basic Page: basic erase-operation write-operation … … (2KB+64 Byte) (2KB+64 Byte) unit. unit. … … … … 511 … … 64MB SLC (2KB+64 Byte) (2KB+64 Byte) Flash Memory

5 5 System Architecture SD, xD, MemoryStick , SmartMedia CompactFlash *FTL: Flash Translation Layer, MTD: Memory Technology Device

6 Policies – FTL • FTL adopts a page-level address translation mechanism . – Main problem: Large memory space requirement Physical Block Address . . (block,page) . . Access LBA = 3 . . 11 1,3 1,2 10 9 (1,3) 1,1 1,0 8 (1,2) 7 0,7 (2,1) 6 (1,0) 0,6 0,5 5 (4,7) 4 (0,4) 0,4 Spare data 0,3 3 (0,6) 2 0,2 LBA=3; 0,1 1 (0,1) ECC=. . .; 0,0 0 (0,3) Status=. . .; Physical Block Logical Block User Spare Address Address data data (block,page) (array index) Address Translation Flash memory Table (in main-memory)

7 Policies – NFTL • Each logical address under NFTL is divided into a virtual block address and a block offset. – e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 = 126 and block offset = 1011 % 8 = 3 NFTL A Primary Block A Replacement Block Address Translation Table Address = 9 Address = 23 (in main-memory) Write data to Free Used LBA=1011 Free Used . Free Used . . Used Free (9,23) Free Free If the page has been . Write to the Block Free Free . used first free page . Offset=3 Free Free VBA=126 Free Free

8 Outline • Introduction • System Architecture • Motivation Motivation • • An Efficient Static Wear Leveling Mechanism • Performance Evaluation • Conclusion

9 Motivation • A limited bound on erase cycles – SLC : 100,000 – MLC x2 : 10,000 • Applications with frequent access – Disk cache (e.g., Robson) – Solid State Disks (SSD) Solid State Disk

10 Motivation – Why Static Wear Leveling: No Wear Leveling Number of Write/Erase Cycles per PBA (75% Static Data) 5000 4000 Erase Cycles 3000 2000 1000 0 20 100 0 40 60 80 Physical Block Addresses (PBA)

11 Motivation – Why Static Wear Leveling: Dynamic Wear Leveling Number of Write/Erase Cycles per PBA (75% Static Data) 5000 4000 Erase Cycles 3000 2000 1000 0 20 100 0 40 60 80 Physical Block Addresses (PBA)

12 Motivation – Why Static Wear Leveling: Perfect Static Wear Leveling Number of Write/Erase Cycles per PBA (75% Static Data) 5000 4000 Erase Cycles 3000 2000 1000 0 20 100 0 40 60 80 Physical Block Addresses (PBA)

13 Motivation – Why Static Wear Leveling is So Difficult? • An intuitive SWL GC starts  find a Update data in block Write new data to Update block 15 GC starts 3 victim block block 4 • Problems: – Block erase 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Flash – Live-page copying memory – RAM space counter 5 5 5 5 4 5 5 4 5 4 5 4 5 5 5 4 5 4 4 5 5 – CPU time : index in the selection of a victim block : index to the selected free block : block contains (some) valid data : free block : dead block

14 Motivation – Comparison No Wear Leveling Dynamic Wear Leveling 5000 5000 Erase Cycles 4000 4000 3000 3000 2000 2000 1000 1000 0 0 20 100 20 60 80 100 0 40 60 80 0 40 Intuitive SWL Intuitive SWL Perfect SWL 5000 5000 Erase Cycles 4000 4000 3000 3000 2000 2000 1000 1000 0 0 20 100 0 40 60 80 0 20 40 60 80 100 Physical Block Addresses (PBA) Physical Block Addresses (PBA)

15 Outline • Introduction • System Architecture • Motivation • An Efficient Static Wear Leveling Mechanism An Efficient Static Wear Leveling Mechanism • • Performance Evaluation • Conclusion

16 Design Considerations in Static Wear Leveling • Scalability Issues – The limitation on the RAM space – The limitation on computing power • Compatibility Issue – Compatibility with FTL and NFTL

17 An Efficient Static Wear Leveling Mechanism • A modular design for compatibility considerations • A SWL mechanism – Block Erasing Table (BET) - bit flags – SW Leveler - SWL-Procedure - SWL-Update

18 The Block Erasing Table (BET) • A bit-array: Each bit is for 2 k consecutive blocks. – Small k – in favor of hot-cold data separation – Large k – in favor of small RAM space e cnt e cnt e cnt e cnt =0 =1 =2 =3 e cnt e cnt e cnt e cnt e cnt =1 =0 =2 =3 =4 f cnt =2 f cnt =2 f cnt =1 f cnt =0 f cnt =1 f cnt =2 f cnt =2 f cnt =0 f cnt =2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Flash 1 BET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 k=0 k=2 e cnt : the total number of block erases done since the BET is reset f cnt : the number of 1’s in the BET : an index to a block that the Cleaner wants to erase : a block that has been erased in the current resetting interval

19 The SW Leveler • An unevenness level (e cnt / f cnt ) >= T  Triggering of the SW Leveler • Resetting of BET when all flags are set. e cnt e cnt e cnt e cnt e cnt e cnt e cnt e cnt e cnt e cnt e cnt =3999 =2998 =2004 =2000 =1998 =1999 =0 =3004 =2999 =4000 =3000 f cnt =4 f cnt =4 f cnt =3 f cnt =3 f cnt =3 f cnt =4 f cnt =3 f cnt =0 f cnt =2 f cnt =2 f cnt =2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T : A threshold, T=1000 in this example e cnt : the total number of block erases since the BET is erased f cnt : The number of 1’s in the BET 1 0 0 0 0 1 1 : An index that SW Leveler triggers the Cleaner to do 1 k=2 garbage collection : An index in the selection of a block set The Cleaner is triggered to : An index to a block that the Cleaner wants to erase Reset to a randomly 1. Copy valid data of selected block set to free area, After a period of time, the total erase 4000 / 4 = 1000>=1000 (e cnt After a period of time, the total erase / f cnt >=1000) selected block set 2. Erase block in the selected block set, and , but all flags in BET are 1  reset BET count reaches 2998. count reaches 3999. (flag) 2000 / 2 = 1000 >= 1000 (E cnt / f cnt >= T) 3000 / 3 = 1000 >= 1000 (E cnt / f cnt >= T) 3. Inform the Allocator to update the address mapping : A block that has been erased in the current resetting interval between LBA and PBA

20 Main-Memory Requirements 512MB 1GB 2GB 4GB 8GB k=0 256B 512B 1024B 2048B 4096B k=1 128B 256B 512B 1024B 2048B k=2 64B 128B 256B 512B 1024B k=3 32B 64B 128B 256B 512B MLC x2 (1 page = 2 KB, 1 block=128 pages)

21 Outline • Introduction • System Architecture • Motivation • An Efficient Static Wear Leveling Mechanism • Performance Evaluation Performance Evaluation • • Conclusion

22 Performance Evaluation • Metrics – Endurance Enhancement (First Failure Time) – Additional Overheads (Extra Block Erases) • Experiment Setup – The FTL Layer - FTL (Flash Translation Layer protocol) - NFTL (NAND Flash Translation Layer protocol) – Traces: - A mobile PC with a 20GB hard disk - Duration: One month. - Daily activities - The average number of Operations: 1.82 writes/sec, 1.97 reads/sec - The percentage of accessed LBA’s: 36.62% – Flash Memory: 1GB MLCx2

23 Endurance Improvement - The First Failure Time When k=3 and T=100, When k=0 and T=100, the endurance is the endurance is improved by 100.2%. improved by 87.5%.

24 Additional Overhead - Extra Block Erases Extra block erases Extra block erases is less than 3%. is less than 2%.

25 Conclusion • An Efficient Static Wear Leveling Mechanism – Small Memory Space Requirement - Less than 4KB for 8GB flash memory – Efficient Implementation - An adjustable house-keeping data structure - An cyclic queue scanning algorithm • Performance Evaluation – Improvement Ratio of the Endurance: - The ratio is more than 50% with proper settings to T and K – Extra Overhead: - It is less than 3% of extra block erase with proper settings - There is limited overhead in live-page copyings

26 Conclusion Control Gate Drain •Future work –Endurance and Source Reliability Problems due to Manufacturing and Capacity I DS Improvements Selected cell - Read/Write Disturbance Problems –System Components - Memory Hierarchy, Devices, Adaptors, etc. –Benchmark Designs - Targets on Different Designs

27 ~ Thank You ~