Embedded Intelligent Systems Edward A. Lee Robert S. Pepper - - PowerPoint PPT Presentation

Embedded Intelligent Systems

Edward A. Lee

Robert S. Pepper Distinguished Professor UC Berkeley

Keynote: ARTEMIS Sprint Event April 13, 2016 Vienna, Austria

ARTEMIS: 2006 Annual Conference, Graz, Austria, May 22-24, 2006

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Industrial automation example from 2008: Bosch-Rexroth printing press. The term “IoT” includes the technical solution “Internet technology” in the problem statement “connect things”. The term CPS does not.

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This Bosch Rexroth printing press is a cyber- physical factory using Ethernet and TCP/IP with high-precision clock synchronization (IEEE 1588) on an isolated LAN.

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The model The target (the thing being modeled).

Solomon Wolf Golomb You will never strike oil by drilling through the map!

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Engineers often confuse the model with its target"

But this does not in any way diminish the value of a map!

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Pierre-Simon Laplace (1749–1827). Posthumous portrait by Joan-Baptiste Paulin Guérin, 1838

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Deterministic model Nondeterministic target

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What kinds of models should we use? Let’s look at the most successful kinds of models from the cyber and the physical worlds.

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Image: Wikimedia Commons

Waterman, et al., The RISC-V Instruction Set Manual, UCB/EECS-2011-62, 2011

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Signal Signal

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Image: Wikimedia Commons

Signal Signal

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Image: Wikimedia Commons

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Correct execution of a program in all widely used programming languages, and correct delivery of a network message in all general-purpose networks has nothing to do with how long it takes to do anything.

Programmers have to step outside the programming abstractions to specify timing behavior. Embedded software designers have no map!

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Timing is not Part of Software and Network Semantics"

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Despite using TCP/IP

• n Ethernet, this

network achieves highly reliable bounded latency. TSN (time-sensitive networks) technology is starting to become pervasive!

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This Bosch Rexroth printing press is a cyber- physical factory using Ethernet and TCP/IP with high-precision clock synchronization (IEEE 1588) on an isolated LAN.

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In engineering, model fidelity is a two-way street! For a model to be useful, it is necessary (but not sufficient) to be able to be able to construct a faithful physical realization.

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Suppose that events flowing in the network are time stamped. Then violations of the assumptions on network latency bounds are detectable, for example.

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This Bosch Rexroth printing press is a cyber- physical factory using Ethernet and TCP/IP with high-precision clock synchronization (IEEE 1588) on an isolated LAN.

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Ptides – A Robust Distributed DE MoC for IoIT Applications

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Proceedings of OSDI 2012

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Time-stamped events that are processed in time-stamp order. This MoC is widely used in simulation and HDLs. Given time-stamped inputs, it is a deterministic concurrent MoC.

A few texts that use the DE MoC

Time stamp value is a deadline Time stamp value is time of measurement Actors wrap sensors Actors wrap actuators

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Ptides: Time stamps bind to real time at sensors and actuators"

Messages are processed in time- stamp order

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See http://chess.eecs.berkeley.edu/ptides

All of the assumptions are achievable with today’s technology, and are requirements anyway for hard-real- time systems. A Ptides model makes the requirements explicit. Lee, Berkeley

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So Many Assumptions?"

You will never strike oil by drilling through the map!

Violations of the requirements are detectable as out-of-order events and can be treated as faults.

Non-Synchronized Clocks

A fault manifests as out-of-order events.

! after an event here with a later time stamp has been processed, then fault! If an event arrives here with an earlier time stamp!

Occurrence

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implies one

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the assumptions was violated. Lee, Berkeley

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Handling Faults"

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The hardware out of which we build computers is capable of delivering “correct” computations and precise timing!

The synchronous digital logic abstraction removes the messiness

• f transistors.

! but the overlaying software abstractions discard the timing precision.

// Perform the convolution. for (int i=0; i<10; i++) { x[i] = a[i]*b[j-i]; // Notify listeners. notify(x[i]); }

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PRET Machines – Giving Software the Capabilities their Hardware Already Has.

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• ! Predictable, REpeatable Timing = PRET
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= PRET +

Computing With time

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http://chess.eecs.berkeley.edu/pret

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Hardware thread Hardware thread Hardware thread

Our Second Generation PRET

PTArm, a soft core on a Xilinx Virtex 5 FPGA (2012)

Hardware thread registers scratch pad memory I/O devices Interleaved pipeline with one set of registers per thread SRAM scratchpad shared among threads DRAM main memory, separate banks per thread memory memory memory

Isaac Liu, PhD Thesis, 2012

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SRT thread Hardware thread Hardware thread Hardware thread Hardware thread

FlexPRET

Hard-Real-Time (HRT) Threads Interleaved with Soft-Real-Time (SRT) Threads

Hardware thread registers scratch pad HRT threads have deterministic timing. SRT threads share available cycles SRAM scratchpad shared among threads DRAM main memory provides deterministic latency for HRT threads. Conventional behavior for the rest. memory memory memory HRT thread Michael Zimmer

Interrupt Handler Thread Hardware thread Hardware thread Hardware thread

FlexPRET I/O

Interrupt-Driven I/O is notorious for disrupting timing

Hardware thread registers scratch pad Interrupts have no effect on HRT threads, and bounded effect on SRT threads! memory memory memory Michael Zimmer

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[Isaac Liu, PhD Thesis, May, 2012]

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.++')+'3.-&"@)'W6).58P"%,-"-=&'&"38".68)"0)" +&'>)'*.02&"2)8-">)'"30.++')+'3.-&" @)'W6).58]"

• ! G3+&63030<P"*&*)'$"=3&'.'2=$P".05"30-&'',+-E

5'37&0"IjD"2.0".66"%&"5)0&"@3-=),-"6)830<" /*30<"5&-&'*30.2$]"

Lee, Berkeley

51

#)026,83)0"

F0"0,-*&*$/1%-'703$%@3-="2*4235%+.*"2+)3% *-G30-0&"./'&$%&O38-">)'"538-'3%,-&5"'&.6E/*&"8$8-&*89"

• ! GJISA1!"538-'3%,-&5"'&.6E/*&"8)c@.'&"

–! S&-&'*3038/2"/*30<".2')88"0&-@)'W8"

• ! G:AJ"*.2=30&8"

–! S&-&'*3038/2"/*30<".-"-=&"+')2&88)'"6&7&6"

Lee, Berkeley

52

We have run out of excuses for sloppy engineering!