E-Beam Lithography Stencil Planning and Optimization With Overlapped - - PowerPoint PPT Presentation

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters

Kun Yuan, David Z. Pan

• Dept. of Electrical and Computer Engineering

The University of Texas at Austin http://www.cerc.utexas.edu/utda

2

Outline

t Introduction and Motivation

› Electronic Beam Lithography (EBL) › Overlapped Characters

t EBL Stencil Planning/Optimization

› One-Dimensional Stencil Design › Two-Dimensional Stencil Design

t Experimental Results t Conclusion

Conventional Optical Lithography

Light source Wafer masks Illumination Lens Projection Lens

4

Scaling Woos

HP

t Aggressive scaling of min. printable half pitch 1

HP k NA λ =

k1: process difficulty NA: numerical aperture λ: wavelength of source t λ is stuck at 193nm t EUV (13.5nm): Still many, many

challenges!

[Smayling+, SPIE 2008]

HP

t k1: limit is 0.25

t NA = 1.5, close to the limit

Mask Cost !!!

Mask 2 Mask 1

Alternative solution for 32nm/22nm and below But mask cost will be proportionally higher! Double Patterning Or even triple/quadruple patterning!

Electron Beam Lithography

Electron Gun Shaping aperture

t Maskless technology, which shoots desired

patterns directly into the silicon wafer

› 4x better resolution [Solid State Technology 2011] › Lower cost [D2S Inc]

The biggest challenge: Low throughput

Variable Shape Beam (VSB)

t One rectangle per shot

Total number of 11 shots are needed

Electron Gun Shaping aperture Electron Gun Shaping aperture

Character Projection (CP) Technology

t Print some complex shapes in one electronic beam

shot, rather than writing multiple rectangles.

Electron Gun Wafer Stencil Shaping aperture

Character

Character Projection Technology (Cont.)

Electron Gun Wafer Stencil Shaping aperture Electron Gun Wafer Stencil Shaping aperture Electron Gun Wafer Stencil Shaping aperture

Only three shots are needed

Limitation of Character Projection

t The number of characters is limited due to the

area constraints of the stencil

› Various investigations [Makoto et al. SPIE’06, SPIE’09] on optimization of character selection Character

W

H

w

h

Overlapped Characters

Layout A Character A Blank A

Spanned region

• f electron beam

from shaping aperture

Layout B Blank B Character B

t Blanking space is usually reserved around its enclosed

rectangular circuit pattern

t By allowing over-lapping adjacent characters, more

characters may be put on stencil [Fujimura+, 2010]

Layout A Layout B Character A Character B Min(BlankA, BlankB) Layout A Layout B Character A Character B BlankA BlankB

Not a Trivial Task

A B C

Stencil Character Candidates to be Considered

A B C A B C

Out of Stencil

Order Matters

Problem Definition

VSB i

n

C

C

i

r

i

t

j

b

min( , )

V ij i j

• t

b =

j

i

i

r

j

l

min( , )

H ij i j

• r l

=

i

j

t Given a set of character candidates

Each candidate appears in the circuit

CP i

n

i

C

#shots by VSB: #shots by CP:

Problem Definition (Cont.)

CP

C

C

C

\

i CP i C CP

CP VSB i i i i C C C C C

rn rn

∈ ∈

+

∑ ∑

A B C

t Select a subset out of character

candidates , and place them on the stencil S

Minimize total number of shots:

While The placement of is bounded by the outline of stencil.

CP

C

Stencil

One Dimensional Problem

t The required blanking spaces on the top t and

bottom b are nearly identical for all the candidates.

• h

h −

W

H

i

j

i

b

i

t

j

b

j

t

=

=

1 1

r

2 1

r

3 1

r

1 2

r

3 2

r

3 2

r

h

• h

Optimization Flow

One-Dimensional Bin Packing Multi Row Swapping Inter-Stencil Tuning Single Row Reordering Result Improved

Yes End No

One-Dimensional Bin Packing

\

( )

i CP i C CP i C i CP

CP VSB i i i i C C C C C VSB VSB CP i i i i i C C C C

rn rn rn r n n

∈ ∈ ∈ ∈

+ = − −

∑ ∑ ∑ ∑

Constant Packing by the decreasing order of

( )

i CP

VSB CP i i i C C

r n n

∈

−

∑

W

…. ….

B A R1 R2 C

W

…. ….

B A R1 R2 C Put C here?

W

…. ….

B A R1 R2 C C S1 S2 <

Put the candidate into the row with most blacking space left Minimize Maximize

Single Row Reordering

t Adjust the relative locations of already-placed

characters in each row to shrink its occupied width and increase remaining capacity

A B C

A B C

Out of Stencil r A

v

r B

v

r C

v

H H big ji

• −

H H big ij

• −

A B C

r A

v

r B

v

r C

v

t Transform to min-cost Hamiltonian path problem

Multi-Row Swapping and Inter-Stencil Tuning

1 1

r

2 1

r

3 1

r

1 2

r

2 2

r

3 2

r

Bigger

R1 R2

1 1

r

2 1

r

3 1

r

1 2

r

2 2

r

3 2

r

Smaller

R1 R2

t Multi-Row Swapping t Inter-Stencil Tuning

› Exchange the placed characters with those which have not been selected

Two Dimensional Problem

1

, are two permutations of characters ( , ... )

n

X Y c c c

t The blanking spaces of templates are non-

uniform along both horizontal and vertical directions.

t Simulated Annealing Framework with Sequential

Pair Representation (... ... ...), =(... ... ...). c is left to c (... ... ...), =(... ... ...). c is below c

i j i j i j j i i j i j

X c c Y c c X c c Y c c = =

Transformation from SP to Stencil

t Transform SP to a min-area packing solution t Pick the candidates within outline of stencil as

characters

A(3) B(2) C(1) D(2)

( ) ( ) X E D A C B Y A B D E C = =

E(2) A(3) B(2) C(1) D(2)

( ) ( ) X E D A C B Y A B D E C = =

E(2)

Throughput-Driven Swapping

t Try to reduce the projection time by swapping

the positions of two candidates in the X &Y SP.

A(3) B(2) C(1) D(2)

( ) ( ) X E D A C B Y A B D E C = =

E(2) A(3) B(2) C(1) D(2) E(2)

( ) ( ) X C D A E B Y A B D C E = =

Stencil Swap C and E

Slack-Base Insertion

t Make use of the concept of slack to find a good

position to insert extra candidate into the stencil

A B A B

left C

X

right C

X

slack right left C C C

X X X = −

D D C C

Slack-Based Insertion

t Make use of the concept of slack to find a good

position to insert extra candidate into the stencil

A B D C

( ) ( ) X E C A D B Y A E C B D = =

E A B C

( ) ( ) X C A D B E Y A C B D E = =

E D

25

Experimental Setup

t Implemented in C++ t Intel 8 Core Linux, 3.0 Ghz, 32GB t Parquet [TVLSI 2003] is adopted as

SA framework

t Compare with two baseline methods

› ILP-based approach without overlap characters [Sugihar, SPIE 2009] › Greedy bin-packing algorithm with

• verlap characters

26

Benchmark

Circuit Character Size

Total area

Total blanks Optimal area 1D-1 3.8x3.8 1.444 0.416 1.028 1D-2 4.0x4.0 1.6 0.479 1.121 1D-3 4.2x4.2 1.764 0.514 1.25 1D-4 4.4x4.4 1.936 0.569 1.367 2D-1 3.8x3.8 1.444 0.414 1.03 2D-2 4.0x4.0 1.6 0.529 1.071 2D-3 4.2x4.2 1.764 0.662 1.102 2D-4 4.4x4.4 1.936 0.774 1.162

um um ×

4 2

1e um

4 2

1e um

4 2

1e um

The area of stencil is 100

100 um um ×

1000 character candidates

27

One Dimensional Stencil Design

10000 20000 30000 40000 50000 1D-1 1D-2 1D-3 1D-4

#shots (projection time)

NON-OVERLAP GREEDY PROPOSED 200 400 600 800 1000 1D-1 1D-2 1D-3 1D-4

#characters on stencil

NON-OVERLAP GREEDY PROPOSED 0.1 1 10 100 1D-1 1D-2 1D-3 1D-4

#CPU(logscale)

NON-OVERLAP GREEDY PROPOSED

t 51%, 14% reduction on shot

number over previous ILP-based approach without overlapping characters and greedy algorithm.

28

Two Dimensional Stencil Design

t 31%, 25% reduction on shot

number over previous ILP-based approach without overlapping characters and greedy algorithm.

29

Conclusion

t E-Beam Lithography is a promising emerging

technology for better resolution and lower cost

t Low throughput is its key hurdle t E-beam lithography stencil planning and

• ptimization with overlapped characters

t Lots of future research opportunities on physical

design and emerging lithography

› E-beam multi-stencil optimization problems › Massive parallel e-beams/characters › Double/triple patterning lithography › EUV, ……

30

Acknowledgment

t The work is sponsored in Part by NSF, IBM

Faculty Award and equipment donations from Intel

t Dr. Gi-Joon Nam at IBM Austin Research Lab for

helpful discussions.