Physical CAD Changes to Incorporate Design for Lithography and - - PowerPoint PPT Presentation

Physical CAD Changes to Incorporate Design for Lithography and Design for Lithography and Manufacturability Manufacturability

Lou Scheffer Cadence Lou Scheffer, Cadence

1 San Jose, 18 Oct 2004

Lou Scheffer

What’s the problem? What s the problem?

• Chip designers and CAD tools have traditionally

Chip designers, and CAD tools, have traditionally worried about

• Logical correctness
• Logical correctness
• Design rule adherence

B t ll l l d i t ll t k

• But all legal designs are not equally easy to make
• New lithography considerations must be followed
• Design features can have a big impact on ease (and

cost, and yield) of manufacturing

• Designing chips to be easy to make is “Design for

Manufacturing”

2 San Jose, 18 Oct 2004

Lou Scheffer

Why now? Why now?

• DFM was always helpful but at sub-100nm
• DFM was always helpful, but at sub-100nm

processes it’s critical

• Sub-wavelength lithography
• New materials

New materials

• Other related issues not covered in this talk
• Timing variation
• Process variation, and yield

y prediction/analysis/improvement

3 San Jose, 18 Oct 2004

Lou Scheffer

Today’s tutorial, part I and II Today s tutorial, part I and II

• Part I: What happens after tapeout?
• Part I: What happens after tapeout?
• Lithography problems
• Manufacturing problems
• Part II: covers the changes to CAD tools to

Part II: covers the changes to CAD tools to address these problems

4 San Jose, 18 Oct 2004

Lou Scheffer

What Happens after Tapeout, and why should you care? should you care?

5 San Jose, 18 Oct 2004

Lou Scheffer

After tapeout, and before chips come back After tapeout, and before chips come back

• You need to make masks and exposures

You need to make masks and exposures

• Masks need optical modification

Th t i l t b t h d

• The material must be etched
• Leads to local density constraints
• The layers must be polished flat
• Leads to more global density constraints

Leads to more global density constraints

• This must be repeated for many layers
• Leads to antenna problems
• How well you do these steps determine yield

6 San Jose, 18 Oct 2004

Lou Scheffer

Masks and Exposure Masks and Exposure

• Long ago we exposed 1 micron (1000 nm)
• Long ago, we exposed 1 micron (1000 nm)

features with 300-400 nm light (relatively easy)

Th k l k d h h l

• The mask looked the same as the polygons
• Now we are exposing 90 nm (and soon 65 nm)

g ( ) features with 193nm light

• Now it looks very different

Now, it looks very different

• Lots of tricks are needed
• Difference between a photo and a hologram

7 San Jose, 18 Oct 2004

Lou Scheffer

Wavelength used vs process generation Wavelength used vs process generation

8 San Jose, 18 Oct 2004

Lou Scheffer

From Numerical Technologies

How a polygon comes out at differing K1, and K1 for different process variations for different process variations

9 San Jose, 18 Oct 2004

Lou Scheffer

Lars Liebmann of IBM

Example of OPC and PSM Example of OPC and PSM

This is what the designer drew Added ‘scattering bars’ and serifs to make the polygon serifs to make the polygon print more exactly Added additional phase features to allow printing features to allow printing smaller features at the same wavelength

10 San Jose, 18 Oct 2004

Lou Scheffer

From Andrew Khang

g

How Phase Shift Masks Work How Phase Shift Masks Work

11 San Jose, 18 Oct 2004

Lou Scheffer

Lots of lithography tricks is an understatement Lots of lithography tricks is an understatement

• Entire conferences journals and working groups devoted

Entire conferences, journals and working groups devoted to this topic

• And sessions at DAC, ICCAD, DATE, ISPD, ASP-DAC and so on

And sessions at DAC, ICCAD, DATE, ISPD, ASP DAC and so on

• SPIE has a MicroLithography symposium each year,

comprised of 6 conferences comprised of 6 conferences

• One of these conferences, Design and Process

Integration specializes in the subjects of this tutorial Integration, specializes in the subjects of this tutorial

• See the SPIE web site: http://www.spie.org

12 San Jose, 18 Oct 2004

Lou Scheffer

New techniques are being developed New techniques are being developed

• Dual mask techniques
• Dual mask techniques
• One prints big features and one sharp edges, or
• One prints horizontal and one vertical edges.
• Lots of new techniques under investigation

Lots of new techniques under investigation

• Attenuated PSM

DDI D bl Di l ill i ti

• DDI – Double Dipole illumination
• CPM – Chromeless Phase Mask
• Each new technique has different limitations

13 San Jose, 18 Oct 2004

Lou Scheffer

Can the process developers bail us out? Can the process developers bail us out?

• Shorter wavelength (157 nm)?

Shorter wavelength (157 nm)?

• This is turning out to be harder than was thought
• C l i

Fl id h t bi f i bl t

• Calcium Fluoride shortages, birefringence problems, etc.
• Immersion lithography?
• Fill the space between the lens and wafer with water
• Light goes slower in water so wavelength is less
• Physics well understood, but lots of practical problems
• Bubbles
• Lens moves over wafer in scanning
• Temperature control

14 San Jose, 18 Oct 2004

Lou Scheffer

RET – Resolution Enhancement Techniques RET Resolution Enhancement Techniques

• If we can’t use a shorter wavelength of light then
• If we can t use a shorter wavelength of light, then

we must use RET (Resolution Enhancement Technology) Technology)

• This is a generic term for modifying the mask so

that it prints better

• Specific cases we have seen are

Specific cases we have seen are

• OPC – Optical Proximity Correction

PSM Ph Shift M k

• PSM – Phase Shift Mask
• Many other techniques are possible

15 San Jose, 18 Oct 2004

Lou Scheffer

OK, so the mask guys are really tricky OK, so the mask guys are really tricky

• But why do I (as a designer) care?
• But why do I (as a designer) care?
• Three reasons:
• Corrections are not complete
• Some designs cannot be built at all with certain RET

Some designs cannot be built at all with certain RET technologies

• Of those that CAN be built some are more

Of those that CAN be built, some are more manufacturable after RET than others

16 San Jose, 18 Oct 2004

Lou Scheffer

Corrections are not complete Corrections are not complete

• If RET worked perfectly, designers could ignore it
• But as we scale down in R, corrections are not

complete complete

Drawn No OPC OPC correction as fabbed

17 San Jose, 18 Oct 2004

Lou Scheffer

Some features cannot be corrected Some features cannot be corrected

Odd Phase cycles Classic example T junction Odd Phase cycles – Classic example, T junction To get minimum width, phases must be opposite

?? Ph

As you go around this circle, you encounter an

?? Phase

circle, you encounter an

• dd number of regions

which require a phase assignment A i

180 Phase 0 Phase

All three lines cannot be minimum width

18 San Jose, 18 Oct 2004

Lou Scheffer

Features that cannot be corrected Features that cannot be corrected

• Just eliminating T junctions does not solve the
• Just eliminating T junctions does not solve the

problem

• Errors can be hard to localize,

much less correct

• What does the designer do if the

OPC tool warns of a cycle of length y g 47?

19 San Jose, 18 Oct 2004

Lou Scheffer

Features that work, but hurt manufacturability Features that work, but hurt manufacturability

• Example – scattering bars

Example scattering bars Scattering bars are these extra lines. They do not extra lines. They do not print themselves but help the other features print with larger process latitude

20 San Jose, 18 Oct 2004

Lou Scheffer

Here is how scattering bars work Here is how scattering bars work

21 San Jose, 18 Oct 2004

Lou Scheffer

From Lars Liebmann of IBM

This leads to ‘forbidden’ pitches This leads to forbidden pitches

22 San Jose, 18 Oct 2004

Lou Scheffer

From Lars Liebmann of IBM

Features that work, but hurt yield Features that work, but hurt yield

• Forbidden pitches are not really forbidden unlike
• Forbidden pitches are not really forbidden, unlike
• dd cycles.
• They will work, but force sub-optimal scattering

bar insertion

• This leads to a smaller process window and

hence more difficult manufacturing, and lower hence more difficult manufacturing, and lower yield

23 San Jose, 18 Oct 2004

Lou Scheffer

Two basic approaches to dealing with RET Two basic approaches to dealing with RET

• Basically knowledge or methodology

Basically, knowledge or methodology

• Knowledge: Designers and/or CAD tools aware of RET,

design around it design around it

• Analog, SRAM, and DRAM folks will do this

Standard Cells may do this

• Standard Cells may do this
• For full custom, it’s a lot to expect of designers, few will do this

Digital designers will never do this

• Digital designers will never do this
• Methodology: Very strict design rules

All i i l di i if i d i i

• All critical dimensions uniform spacing and one orientation
• Mask must be a subset of a uniform grating

24 San Jose, 18 Oct 2004

Lou Scheffer

Etching and polishing Etching and polishing

• Even if we can expose the wafer with the right
• Even if we can expose the wafer with the right

shape, we are not done yet

• Still need to build and etch the metal, then polish

it flat so we can build the next layer

• Etching – local loading effects
• Polishing

more global effects

• Polishing – more global effects
• CMP – Chemical Mechanical Polishing

25 San Jose, 18 Oct 2004

Lou Scheffer

CMP – Chemical Mechanical Processing CMP Chemical Mechanical Processing

26 San Jose, 18 Oct 2004

Lou Scheffer

From Fraunhofer Institute web site

Etching and CMP Etching and CMP

• Etching Problems

Etching Problems

• Plasma becomes more heavily loaded in regions of

high density high density

• This is a relatively short range effect (a few microns)
• Polishing Problems
• Polishing Problems
• Oxide and metal are different hardnesses
• Therefore they etch at different rates
• This occurs over hundreds of microns
• Solution: Try to keep density constant over all

scales

27 San Jose, 18 Oct 2004

Lou Scheffer

Problems with CMP: Erosion and dishing Problems with CMP: Erosion and dishing

Dishing – a wide Erosion – a density g wire problem y related problem Metal Dielectric

28 San Jose, 18 Oct 2004

Lou Scheffer

Solution – keep density uniform Solution keep density uniform

• Keep density from getting too high by adding
• Keep density from getting too high by adding

‘wide wire’ rules

• Keep density from getting too low by adding

‘metal fill’

• But these clearly impact

Coupling

• Coupling
• Critical area
• Yield

29 San Jose, 18 Oct 2004

Lou Scheffer

Metal Spacing and Density (cont) Metal Spacing and Density (cont)

Maximum density rules “helped” by wide-wire spacing rules Maximum density rules helped by wide wire spacing rules

• Implicitly enforces a local density rule
• Helps global density but no guarantee
• Helps global density, but no guarantee
• Also helps with etch loading

Width Spacing Max Density 0.15um 0.15um 50-60% 0.22um 0.20um 52-88% 1 50um 0 50um 75-90% 1.50um 0.50um 75-90% 4.50um 1.5um 75-83% 7 50um 2 5um 75 83%

30 San Jose, 18 Oct 2004

Lou Scheffer

7.50um 2.5um 75-83%

Metal Spacing and Density (cont)

New Vicinity/Influence rule (two versions) New Vicinity/Influence rule (two versions)

>W X H X X H X X W W M <=W H W M M <=W

Error

M

M: min spacing X: extra spacing H h l i

31 San Jose, 18 Oct 2004

Lou Scheffer

H: halo size W: wide-wire width

Metal Spacing and Density (cont) Metal Spacing and Density (cont)

Local density rules enforced by wide-wire vicinity rules Local density rules enforced by wide wire vicinity rules

• values vary even inside same consortium
• helps global density but no guarantee
• helps global density, but no guarantee

Width Halo Spacing p g 0.15um NA NA 0 22um 0 20* 0 20* 0.22um 0.20 0.20 1.50um 0.50um 0.50um 4 50 1 5 1 50 4.50um 1.5um 1.50um 7.50um 2.5um 2.50um

*may be removed

32 San Jose, 18 Oct 2004

Lou Scheffer

*may be removed

Via Void Problems

• Copper processing causes new problems for vias

Coppe p ocess g causes e p ob e s o as

• Voids in Cu migrate under thermal stress towards vias

If h id i t t i it f il

• If enough voids migrate to a via it can cause failure
• worse at 90/65nm due to increased stress of smaller via

Voids can migrate long distances Voids can i d long distances ~10 microns migrate around corners

33 San Jose, 18 Oct 2004

Lou Scheffer

Via Void rules Via Void rules

• To keep reliability acceptable need more vias
• To keep reliability acceptable, need more vias
• Need 2, 3 or 4-cut vias when connect to wide-metal
• Does not depend on the current carried

applies to “close connections” applies to close connections

• f wire-wires also

34 San Jose, 18 Oct 2004

Lou Scheffer

Antenna rules Antenna rules

• Antenna rules have nothing to do with traditional
• Antenna rules have nothing to do with traditional

definition of antenna

R ll ll f i h l i

• Really a collector of static charge, not electromagnetic

radiation

• Only happens during manufacturing
• Problem introduced with plasma etching, many

Problem introduced with plasma etching, many process generations ago

• N t

bl b t b 100 t i l

• Not a new problem, but sub-100nm materials

may make it a lot worse

35 San Jose, 18 Oct 2004

Lou Scheffer

Antenna Rules – a Review Antenna Rules a Review

• A long line connected to gate only can

A long line connected to gate only can cause failure

• Not a problem after chip is complete since

every net has at least one driver

M2 M1 Driver (diffusion) Load (poly)

36 San Jose, 18 Oct 2004

Lou Scheffer

Antenna Rules Antenna Rules

• But we can have a problem during

But, we can have a problem during manufacturing f

• Here is the same net after M1 is built, but

not yet M2

• Error!

M1 Driver (diffusion) Load (poly)

37 San Jose, 18 Oct 2004

Lou Scheffer

Gate leakage and materials Gate leakage and materials

• Gate leakage is helpful for antenna problems

Gate leakage is helpful for antenna problems

• Leakage does not hurt the oxide

K lt f tti t d l l

• Keeps voltages from getting to dangerous levels
• Thin oxide has higher area ratios allowable
• But gate leakage is creating horrible standby

power problems

• Process engineers are trying to switch to high-K

materials to help the standby leakage problem p y g p

• But this will (probably) make the antenna

problem much worse!

38 San Jose, 18 Oct 2004

Lou Scheffer

problem much worse!

Why high K for gates? Why high K for gates?

• High K allows thicker gate oxide

High K allows thicker gate oxide

• Here’s the cross section of a transistor
• High K material replaces the SiO2 of conventional gates

SiO2 High K Gate Diffusion Channel Transistor with high K gate oxide

39 San Jose, 18 Oct 2004

Lou Scheffer

Why high K? Why high K?

• Capacitance is the same
• Capacitance is the same
• No additional loading on prior gates
• Field at the edge of the dielectric is the same
• Transistors have the same performance

Transistors have the same performance

• Dielectric is much thicker
• Leakage is reduced exponentially (to negligible levels)
• Great in theory, but a hard material problem

Great in theory, but a hard material problem

• Must be easy to make and reliable

40 San Jose, 18 Oct 2004

Lou Scheffer

Conclusions Conclusions

• A lot happens between tapeout and working
• A lot happens between tapeout and working

chips coming back

M k ki

• Mask making
• Etching
• Polishing
• Stacking layers

Stacking layers

• New materials cause new problems
• Designs can help or hinder these efforts

41 San Jose, 18 Oct 2004

Lou Scheffer

CAD Tool Changes for sub 100nm Lithography and Manufacturability Lithography and Manufacturability

42 San Jose, 18 Oct 2004

Lou Scheffer

Outlined a number of mfg problems Outlined a number of mfg problems

• OPC rules
• OPC rules
• Metal density
• Local and global
• Antenna rules

Antenna rules

• In general, three approaches to new rules:
• Design tools (and designers) know about these

problems

• Post processing corrects these problems
• Methodology changes to avoid these problems

43 San Jose, 18 Oct 2004

Lou Scheffer

Methodology changes to avoid these problems

Rules in general are more complex Rules in general are more complex

• There are roughly 600 design rules for a typical

There are roughly 600 design rules for a typical 90 nm process

• Example: Wide wire spacing rules
• Example: Wide wire spacing rules
• These must be understood by the router
• Cannot be fixed by post-processing
• In addition, many ‘recommended rules’ that

y affect manufacturability

• Extra spacing if room available

p g

• Redundant vias if possible
• Extra enclosure around contacts if possible

44 San Jose, 18 Oct 2004

Lou Scheffer

Extra enclosure around contacts if possible

OPC driven changes OPC driven changes

• Downstream OPC usually requires limitations on
• Downstream OPC usually requires limitations on

geometries

• Exact limitation depends on OPC chosen
• OPC for 90nm is already decided and factored into

y design rules. Mainly impacts the poly mask.

• OPC, and mask technology, for 65 nm node is

OPC, and mask technology, for 65 nm node is still unclear

45 San Jose, 18 Oct 2004

Lou Scheffer

Metal OPC Rules

• Small steps cannot be “fixed” by OPC rules
• add commands to fill in the gap, then do spacing check

min “concave” step

k fill it in

• k

serifs “collide”

mask-shop adds serifs to avoid “lost corners”

serifs collide creating illegal shape

46 San Jose, 18 Oct 2004

Lou Scheffer

Phase shift rules Phase shift rules

• Depends on whether you have dark field or light

p y g field exposures

• Assign phases to the gaps or the polygons

g p g p p yg

• Where you cannot get good phase assignment,

need to use larger rules need to use larger rules

• In general, cannot fix violations (at least well) by

post processing post processing

• Therefore, routers (and designers) must

d t d th t i t understand these constraints

• New tool – “Phase compliance checker” to see if

47 San Jose, 18 Oct 2004

Lou Scheffer

phase assignment is possible

An Alternative: Methodology fixes An Alternative: Methodology fixes

• Lars Liebman of IBM is the champion of the school that

Lars Liebman of IBM is the champion of the school that proposes very strict methodology

• We don’t know what lithography will win at 65 and 45 nm

We don t know what lithography will win at 65 and 45 nm

• Immersion, PSM, double dipole, etc.
• Each lithograph method has different limitations
• Each lithography method has different limitations
• But all proposed techniques are good at equally spaced

li d ( ti ) lines and spaces (a grating)

• Therefore, build your layout (at least the critical masks) to

l k h lik ti ibl look as much like a grating as possible

• All critical dimensions in one direction and equally spaced.

48 San Jose, 18 Oct 2004

Lou Scheffer

Example of a ‘strict’ methodology design Example of a strict methodology design

• All transistors are

horizontal

• All gates on a common

pitch

• All wrong way routing

uses wider (non-critical) dimensions

• Easy to assign phases

y g p

• But won’t this cost

area?

49 San Jose, 18 Oct 2004

Lou Scheffer

area?

Source: Lars Liebmann of IBM

Not clear if this costs any area! Not clear if this costs any area!

50 San Jose, 18 Oct 2004

Lou Scheffer

Source: Lars Liebmann of IBM

Metal Spacing and Density Metal Spacing and Density

• Caused by CMP (Chemical Mechanical Polishing)

y ( g)

• metal and dielectric thickness varies due to metal

density (thickness varies by +/- 30% without rules) y ( y )

• Multiple density rules for different window sizes

20% to 70% for 100x100um windows

• 20% to 70% for 100x100um windows
• 20% to 65% for 500x500um windows
• minimum met by adding dummy metal (metal fill)
• maximum “helped” by wide-wire spacing rules
• local maximum density enforced by spacing rules
• Need new verification commands check/fix densities

51 San Jose, 18 Oct 2004

Lou Scheffer

• rules keep thickness variation to ~ +/- 10%

Several different methods for density control Several different methods for density control

• Who does the fill?
• The router?
• A post-processor?

p p

• How do we do the fill?

Add patterns of rectangles

• Add patterns of rectangles
• Add wires
• Handling maximum width rules
• What do you do if the density is too high?

y y g

• Target a density versus meeting the rules

R t l t ( d k t) i ld

52 San Jose, 18 Oct 2004

Lou Scheffer

• Rectangle count (and mask cost) versus yield

Metal fill to fix low densities

Traditional Metal Fill Method – Done by Post-Processing Alternative Metal Fill Method – Done by the Router

W

Done by Post-Processing Done by the Router

VSS FA W FA VSS FA S Active Geometry W - Width of fill FA Fill to active W W – Variable Width Fill Geometry FA – Fill to active spacing S –Fill Spacing W Next Layer

53 San Jose, 18 Oct 2004

Lou Scheffer

Conflict between vendors and designers

Pros and cons of post-processing for fill Pros and cons of post processing for fill

• Traditional (post-processing) fill requires no help
• Traditional (post-processing) fill requires no help

from the router

W k bi d i

• Works on arbitrary designs
• However, it introduces uncertainty in timing

y g

• Minimized by keeping the fill far from nets
• And uncertainty in coupling
• And uncertainty in coupling
• Since the inserted metal is floating

54 San Jose, 18 Oct 2004

Lou Scheffer

Pros and Cons of router-created fill Pros and Cons of router created fill

• Fewer polygons
• Fewer polygons
• Most inserted polygons are grounded
• Helps crosstalk rather than hurts it
• Fill geometry and effects are known when the

Fill geometry and effects are known when the designer does extraction

Thi i i l i th t’ h th b

• This is crucial, since that’s when they can be

corrected

• But the router must be smarter
• Insert fill, grounded fill, remove fill for ECO, etc.

55 San Jose, 18 Oct 2004

Lou Scheffer

, g , ,

Smarter extraction Smarter extraction

• Even after fill density will not be completely
• Even after fill, density will not be completely

uniform

IP bl k RAMS f b dj d

• IP blocks, RAMS, etc. often cannot be adjusted.
• Metal thickness in general depends on density

g y

• Wide wires suffer dishing

R d d th idth

• R per square depends on the width
• Need extractor technology that handles CMP

effects

56 San Jose, 18 Oct 2004

Lou Scheffer

Maximum Width rules Maximum Width rules

• Due to thermal

Due to thermal stress and local density rules

GND GND

density rules

• Maximum wire width

can be q ite small

GND GND GND

can be quite small

> 2.5um needs slots in

M1 M1

some 90 nm processes

• Post-layout slotting

versus “bus” of thin

57 San Jose, 18 Oct 2004

Lou Scheffer

wires

Pros and cons of slotting as a post process Pros and cons of slotting as a post process

• Advantages of adding slots as a post-process

Advantages of adding slots as a post process

• Easy on the designer

P ti t l d t d t b t

• Power routing tools do not need to worry about

maximum width rules Manual editing of routes is easy they are simply a

• Manual editing of routes is easy – they are simply a

very wide wire at this stage

• Disadvantages:
• Disadvantages:
• Slots may not be aligned with current flow
• Via arrays are very hard to correct
• True IR drop not known until after slotting

58 San Jose, 18 Oct 2004

Lou Scheffer

Pros and Cons of Slotting by the Power Router Pros and Cons of Slotting by the Power Router

• More difficult for power router

More difficult for power router

• Needs to understand maximum width rules
• Needs special understanding for manual editing

Needs special understanding for manual editing

• Must understand a bundle of small wires is a single construct
• However IR drop is becoming more critical

However, IR drop is becoming more critical

• Lower VDD
• Higher power

Higher power

• Slots are aligned with the current flow
• Via arrays are handled very naturally

Via arrays are handled very naturally

• Router driven slots lets designers fix problems

59 San Jose, 18 Oct 2004

Lou Scheffer

Dealing with Maximum Density rules Dealing with Maximum Density rules

• What if your maximum density is too high?
• What if your maximum density is too high?
• This can happen if you (for example) have a bus
• f wide wires.
• No plausible post-processing can fix this

No plausible post processing can fix this

• Tools must be aware of this limitation

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Lou Scheffer

Antenna rule driven changes Antenna rule driven changes

• Antenna rules very difficult to check by
• Antenna rules very difficult to check by

geometrical operations alone

• Need connectivity understanding
• Necessity will depend on when high K gates are

Necessity will depend on when high K gates are introduced

Situation will get better (thinner oxides) until it

• Situation will get better (thinner oxides) until it

suddenly gets much worse (high K materials).

61 San Jose, 18 Oct 2004

Lou Scheffer

Antenna Rules – a review Antenna Rules a review

• A problem during manufacturing
• A problem during manufacturing
• Here is a net after M1 is built, but not yet

M2

• Error!

Error!

M1 Driver (diffusion) Load (poly)

62 San Jose, 18 Oct 2004

Lou Scheffer

Antenna Rules – what can tools do? Antenna Rules what can tools do?

• Possible solution – reverse order of layer

Possible solution reverse order of layer assignments Ch l l l tili ti

• Changes local layer utilization

M2 M1 Driver (diffusion) Load (poly)

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Lou Scheffer

Antenna Rules – what can tools do? Antenna Rules what can tools do?

• Another possible solution
• Little change of routing but adds vias

Little change of routing, but adds vias

This layer change added at g the input M1 M2 Driver (diffusion) Load (poly)

64 San Jose, 18 Oct 2004

Lou Scheffer

( ) (p y)

Antenna Rules Antenna Rules

• After M1 we have floating nodes, but that’s

OK

M1 Driver (diffusion) Load (poly)

65 San Jose, 18 Oct 2004

Lou Scheffer

Antenna Rules – what can tools do? Antenna Rules what can tools do?

• A third possible solution

add diodes

• A third possible solution – add diodes
• Will probably be required by high K rules
• But introduces more via blockage (and

performance penalty) performance penalty)

M2 M1 Driver (diffusion) Load (poly) Added Diode

66 San Jose, 18 Oct 2004

Lou Scheffer

Avoiding antenna problems Avoiding antenna problems

• Fix antenna problems with the router

Fix antenna problems with the router

• Highest performance, but can’t always be done

R i th t d t d th t l

• Requires the router understand the antenna rules
• Add diode cells after routing for those nets that

t b fi d cannot be fixed

• Still requires some router smarts
• Add diodes to each input
• This is a “methodology” fix

This is a methodology fix

• Requires no tool smarts

Lowest performance option extra C and extra area

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Lou Scheffer

• Lowest performance option – extra C and extra area

Antenna rules Antenna rules

• The routing corrections cannot be added by
• The routing corrections cannot be added by

post-processing.

Th d d h l

• The router must understand these rules
• Adding diodes as separate cells requires some

g cooperation from the router

• Adding a diode to each input avoids the problem

Adding a diode to each input avoids the problem

• Lowest performance
• But no tool changes required

68 San Jose, 18 Oct 2004

Lou Scheffer

Recommended rules and optimizations Recommended rules and optimizations

• Foundries have additional ‘recommendations’

Foundries have additional recommendations

• Double vias where possible

Add t i h ibl

• Add extra spacing where possible
• Add more extension around vias where possible
• Help from foundries is needed to make this quantitative
• Some of this can be done by post-processing

y p p g

• But much better results possible if tools do it

Example What percentage of vias can be doubled?

• Example – What percentage of vias can be doubled?
• 30-40% as a post-process, more than 90% if router tries

hard

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hard.

Router can help make RET easier Router can help make RET easier

• Can choose correction based on need (SPIE)
• Can choose correction based on need (SPIE)

Line end at minimum spacing p g perhaps 5-10 extra rectangles required Slightly greater spacing – 2 rectangles required Still t i t i Still greater spacing – extension

• nly required

Si l ti b d OPC ill t ll t th hi h t ( t

70 San Jose, 18 Oct 2004

Lou Scheffer

Simulation based OPC will correct all to the highest (most expensive) standard

Conclusions Conclusions

• Post processing is the most convenient fix
• Post processing is the most convenient fix
• But it works in fewer and fewer cases
• Tools (and designers) need understanding of

downstream effects for best results

• OPC

Metal density

• Metal density
• Antenna
• A new generation of tools will handle these effects
• Methodology changes may be required as well

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Methodology changes may be required as well