DPM Upgrade status Fibre trays Firmware R&D DUNE DAQ Hardware - - PowerPoint PPT Presentation

DPM Upgrade status Fibre’ trays Firmware R&D

DUNE DAQ Hardware Meeting

24 24 May2018

1 Babak Abi, DAQ meeting

DPM Upgrade, , curr rrent status

• DPM (RCE already proven performance in 35t & ProtoDUNE):
• Xilinx Zynq Ultrascale FPGA (xczu15eg_ffvb1156) + 16GB DDR4-2666 Memory
• Resource per APA:
• ~3m System Logic Cells, 16xCPU (ARM A53)+8xARM(R5), 96xGTH 16.3Gb/s
• SSD on M.2 Next Generation Form Factor (NGFF) Connector
• 18 Layer PCB, 110mm by 88mm approx, Designed to fit SLAC COB
• 10s pre-trigger buffer + 10minutes Post-trigger buffer
• Plan& schedule : 25 April 2018: plan in progress as scheduled

1. System design and schematics, already done(SLAC&Oxford) 2. PCB layout – (High speed & dense PCB) (final review end of June 2018) 3. Signal integrity check (DDR4 and 10Gb/S+ ) 4. Prototyping (September 2018) a) PCB manufacturing x b) Components ordering (long lead time ) c) Assembly 5. Firmware and tests (SLAC + Oxford + ?…)

• Oct 2018, firmware developer are very welcome

2 Babak Abi, DAQ meeting Component Cost(£) FPGA 2000 RAM 320 PCB 200 Assembly 250 Other components 200 Cost per DPM (price for 6 ) 2970(£)

Status : (Peter Hastings) 25 April 2018 PCB layout (DDR4 and 10Gb lanes) in progress. Planning for test stand and test firmware (in progress). Placed order for DDR4 chips, need to place order for FPGA (long lead time we will receive the DDR4 chips 1st August 2018)

DPM Upgrade status

• 3

Babak Abi, DAQ meeting

(Peter Hastings, 25 April 2018) SLAC/OXFORD Board layout design – Oxford DPM Single Zynq Ultrascale+ PCB Design Peter Hastings 24 May 2018

PCB stack has been change and whole board re-routed again

DPM status and schedule

• Layout Produced Using Mentor Graphics

Xpedition VX.2.3

• Board stack up implemented giving greater control
• f impedances on certain traces (DDR4/Gigabit

signalling) for both differential and single ended

• traces. Now at the stage of simulating and tuning

nets to meet compliance for fast signals.

• Stack up developed in unison with Express

Circuits Group to ensure a UK based PCB manufacturer can actually build the design.

• High Speed traces are being compliance

checked using Hyperlynx VX.2.3

• This is still a work in progress but we aim to make

the PCIE Gen 2 lines compliant with Gen 3

• standards. All DPM signals are 10GBit Ethernet
• compliant. We will be using this tool to check DDR4

routing.

• Still in schedule,
• The PCB will be ready for review first week of June.

4 Babak Abi, DAQ meeting

Peter Hastings 24 May 2018

Quick estimation for

• Quick look/estimation fibers trays or duct between CUC and cavern
• Size and weight (per meter)
• Do we have patch panels ?
• Do we have safe environment to use non-armoured cable ?
• Do we need to follow any Mine Safety Certification or standard?
• Like MGTSV Mining Flame-retardant

5 Babak Abi, DAQ meeting

150 APA CUC Patch panel

Servers

Patch panel

We only estimate the size and weight that trays have to handle between CUC and cavern. ( no talk about Inside the cavern or CUC room ) There might be more cables, like CAT6! and other subsystems like timing PDS ….

• so can use 144 fibre cable:
• MGTSV class: Mining Fiber Optical Cable Used in Harsh Environment
• With flame retardant and rodent resistance property, it is suitable for coal, gold, iron ore and
• ther mines applications.

6 Babak Abi, DAQ meeting

Rate Gbps # Links/APA #Link/10kt #Cable/10kt Weight Kg/m Rectangular size cm 1.25 80 12000 84 59 25 2.5 40 6000 42 30 18 5 20 3000 21 15 13 10 10 1500 11 8 9

The usual Weights of LSZH cables are half of this, this is example of the heaviest cables

Weight Kg/m Rectangular size cm 27 19 14 13 7 10 4 7

Assuming we do have patch panel

Assuming we do not have patch panel

• so can use 12 fibre cable LSZH :
• MGTSV class 12

7 Babak Abi, DAQ meeting

Rate Gbps # Links/APA #Link/10kt #Cable/10kt Weight Kg/m Rectangular size cm 1.25 80 12000 1000 38 19 2.5 40 6000 500 19 14 5 20 3000 250 10 10 10 10 1500 125 5 7 Weight Kg/m Rectangular size cm 150 38 75 27 38 19 19 14

The armoured cable might have weight issue in case of 12 fiber/cable

DPM (F (FPGA fir firmware) High-level data flow diagram

https://docs.google.com/document/d/1prjeq0AiturRpx4egD7BXm_yLSNxE5V4j rxhf0XAq6U/edit?usp=sharing

8 Babak Abi, DAQ meeting

DPM / FPGA fir firmware R&D

• High-level data flow diagram for an FPGA based

system

• To go to more detail we need to answer some more

questions like :

• What is the trigger primitive parameters to be send out?
• Additional block diagrams like bad channels masking ? Or

data treatment

• …………

Need people for firmware ->

9 Babak Abi, DAQ meeting

Sub Projects How much exist already Wher e 1-CORE PS/PL Ryan/Larry 2-Compression PL J.J. 3-TPC Interface PL ? 4-Data Splitter PL ? 5-Filter PL Roy, Babak, Peter 6-Hit Finder PL J.J. 7-10GE(TCP) In core PL/PS ? 8- Buffer controller - DDR4 PL/PS ? 9- Buffer controller - SSD PS Roy, Babak, Peter 10-GE(serial FELIX) PL ? 11- PS C++ PS ? Time/Trigger Block PL Bristol + ?