Sig ignal In Integrity Checks Ba Babak Abi 30 August 2018 1 - - PowerPoint PPT Presentation

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Sig ignal In Integrity Checks Ba Babak Abi 30 August 2018 1 - - PowerPoint PPT Presentation

Feb 27, 2023 130 likes •373 views

DPM Status update Sig ignal In Integrity Checks Ba Babak Abi 30 August 2018 1 DPM Design simply includes : ZYNQ: XCZU15EG-1FFVB1156E samtec M2 NMVe DDR4 : MT40A1G16WBU-083(twin die) in two separate banks 1. 4x DDR4 (8 GB)

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DPM Status update Sig ignal In Integrity Checks

Ba Babak Abi

30 August 2018

1

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DPM Design simply includes :

  • ZYNQ: XCZU15EG-1FFVB1156E
  • DDR4 : MT40A1G16WBU-083(twin die) in two separate banks

1. 4x DDR4 (8 GB) connected to PL 2. 4x DDR4 (8 GB) connected to PS

  • M.2 NMVe: 512 GB on DPM connected to PCIe Gen2 on top of

DDR4s

  • Dimensions: 89 mm x 110 mm
  • 24 GHT TX and 24 GTH RX connecte to 2 samtec connecter
  • PCB stack is 20 layers
  • We would like to have review on signal integrity check

particularly for the DDR4 delays. The GTH and PCie are pretty under control.

  • If anybody interested to do review we can provid the board’s

Hyperlinx file, schematic, a ibis for ZYNQ and DDR4. ZYNQ’s pin flight-times in excel. ZYNQ M2 NMVe DDR4 PL DDR4 PS samtec samtec

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U7 ZYNQ

XCZU15EG

PCIe Gen2 J6 connector U12 DDR4 U14 DDR4 U13 DDR4 U15 DDR4 termi natio n

Address/Command/...

U16 DDR4 U18 DDR4 U17 DDR4 U19 DDR4 termi natio n

DATA,DQ,DQS.. 24 GTH @10GE

PS PL

48 TX/RX 10GB/s

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PCB stack up 20 layers – no back drill

samtec

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PCB stack up 20 layers – no back drill

samtec 20 layers but still very busy board

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GTH lines Compliance: COM (10GBASE-KR)

All passes 10GBASE-KR

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GTH lines Compliance: plots1

  • Insertion loss and Fitted attenuation are important
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GTH lines Compliance: plots 2

  • Some of near end RL are a bit higher the we like: even it is not

important but we would like to fix them to reduce risk of failure due to impedance deviation in PCB manufacturing

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Long Stub

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VIA stubs 3D simulation

Many simulation with different via structure is done to get the best via for each GTH line

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SerDesResults_20180815-0200 SerDesResults_20180817-0157 C:\work\dpm_lmb_zynq_ultrascale_c01\Output\SerDesResults_20180817-0157 Before After

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After Before

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After Before

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Backup

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GTH lines Compliance COM (10GBASE-KR) bit sequences

From file : DDR4_lineSIM_MEM_A4_ZYNQ_PL_MEM.ffs

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TDR impedance TX0 Line

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Overshooting through Dadd

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