Developing Fault Models for Nanowire Logic Circuits D. Gil, D. de - PowerPoint PPT Presentation

Developing Fault Models for Nanowire Logic Circuits D. Gil, D. de Andrés , J.-C. Ruiz, P. Gil { dgil, ddandres, jcruizg, pgil} @disca.upv.es

2 Outline � Introduction � NW-based logic circuits � Fault models at device level � Fault models at logic level � Conclusions and challenges

3 Outline � Introduction � NW-based logic circuits � Fault models at device level � Fault models at logic level � Conclusions and challenges

4 Emerging research information processing devices Conventional scaled CMOS New information process technologies

5 New information process technologies FET Extensions 1D Channel Ferromagnetic Device SET Molecular Spin transistor structures replacement logic CNT FET Crossbar Spin Gain NW FET latch III-IV compound transistor NW hetero- Typical Moving domain wall semiconductor and Molecular SET Spin FET structures Ge channel transistor examples M: QCA Spin Torque Nanorribon replacement Molecular transistor transistors with QCA graphene Research 379 62 91 244 32 122 activity

6 Methodology NW-based logic circuits Fault manifestation NW-based devices Nanowires Manufacturing defects

7 Outline � Introduction � NW-based logic circuits � Fault models at device level � Fault models at logic level � Conclusions and challenges

8 Electronic devices with NWs � NW-FET � Diode

9 NW-based AND gate

10 NW-based OR nanoPLA plane with signal restoration Programmable Signal restoration circuit crosspoints

11 Outline � Introduction � NW-based logic circuits � Fault models at device level � Fault models at logic level � Conclusions and challenges

12 Manufacturing defects Defect Cause/ Mechanism Effect Mechanical stress during Open I/O connections, p-n Broken assembly junctions or FET channel Nanowire Poor Statistical number of atomic Increase of wire resistance defects contacts scale bounds Doping Statistical doping Variation of wire resistance variation Open in diodes or NWFETs Open Non-programmable crosspoints Crosspoint Statistical junction formation defects with tens of molecules Short in diodes and NWFETs Short Shorted crosspoints Imperfect planar NW alignment Shorts between I/O connections or Bridging of adjacent nanowires device terminals Variations in core shell thickness

13 Fault models at device level (manufacturing defects) Causes and mechanisms Fault models at device level (manufacturing defects) Diodes FETs I / O connections Broken wires open open open Nanowire defects Poor contacts delay delay delay Doping variation delay delay delay Open crosspoint open/missing* open - Crosspoint defects Short crosspoint short/extra* * short - Imperfect alignment short short short Bridging of adjacent Shell thickness nanowires short short short variations * In programmable circuits: missing devices due to permanent off crosspoints ** In programmable circuits: extra devices due to permanent on crosspoints

14 Outline � Introduction � NW-based logic circuits � Fault models at device level � Fault models at logic level � Conclusions and challenges

15 Fault models at logic level � Hierarchical structure � Logic circuit made of devices made of NWs � Single faults � For each device in the structure � � For each fault model at device level � � Analyse the fault propagation to the circuit’s output

16 Fault models at logic level Example 1: AND gate

17 Fault models at logic level Example 1: AND gate

18 Fault models at logic level Example 1: AND gate

19 Fault models at logic level Example 2: Programmable circuits

20 Fault models at logic level Example 2: Programmable circuits

21 Outline � Introduction � NW-based logic circuits � Fault models at device level � Fault models at logic level � Conclusions and challenges

22 Conclusions � Definition of fault models for nanowire-based logic circuits � Bottom-up methodology � Physical � Device � Logic � The methodology can be applied to other nanodevices and architectures

23 Challenges � Modelling a wider set of faults � Wearout faults � Transient faults � Multiple faults � Fault models for other nanodevices � CNT, molecular, spintronics, … � Dependability assessment of emerging (fault/defect tolerant) nanoarchitectures

24 paying attention! Thank you for Any question?

Developing Fault Models for Nanowire Logic Circuits D. Gil, D. de Andrés , J.-C. Ruiz, P. Gil { dgil, ddandres, jcruizg, pgil} @disca.upv.es