Developing Fault Models for Nanowire Logic Circuits D. Gil, D. de - - PowerPoint PPT Presentation
Developing Fault Models for Nanowire Logic Circuits D. Gil, D. de Andrs , J.-C. Ruiz, P. Gil { dgil, ddandres, jcruizg, pgil} @disca.upv.es 2 Outline Introduction NW-based logic circuits Fault models at device level Fault
{ dgil, ddandres, jcruizg, pgil} @disca.upv.es
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Introduction NW-based logic circuits Fault models at device level Fault models at logic level Conclusions and challenges
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Introduction NW-based logic circuits Fault models at device level Fault models at logic level Conclusions and challenges
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Conventional scaled CMOS New information process technologies
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Research activity Typical examples Device
122 32 244 91 62 379 Spin Gain transistor Spin FET Spin Torque transistor Moving domain wall M: QCA Crossbar latch Molecular transistor Molecular QCA SET III-IV compound semiconductor and Ge channel replacement CNT FET NW FET NW hetero- structures Nanorribon transistors with graphene
Spin transistor Ferromagnetic logic Molecular SET Channel replacement 1D structures FET Extensions
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NW-based logic circuits NW-based devices Nanowires
Manufacturing defects
Fault manifestation
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Introduction NW-based logic circuits Fault models at device level Fault models at logic level Conclusions and challenges
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Diode NW-FET
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Signal restoration circuit Programmable crosspoints
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Introduction NW-based logic circuits Fault models at device level Fault models at logic level Conclusions and challenges
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Shorts between I/O connections or device terminals Imperfect planar NW alignment Variations in core shell thickness Bridging of adjacent nanowires Short in diodes and NWFETs Shorted crosspoints Short Open in diodes or NWFETs Non-programmable crosspoints Statistical junction formation with tens of molecules Open Crosspoint defects Variation of wire resistance Increase of wire resistance Open I/O connections, p-n junctions or FET channel
Effect
Statistical doping Doping variation Statistical number of atomic scale bounds Poor contacts Mechanical stress during assembly Broken Nanowire defects
Cause/ Mechanism Defect
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short short short Shell thickness variations short short short Imperfect alignment Bridging of adjacent nanowires
short/extra* * Short crosspoint
Open crosspoint Crosspoint defects delay delay delay Doping variation delay delay delay Poor contacts
Broken wires Nanowire defects
I / O connections FETs Diodes Fault models at device level Causes and mechanisms (manufacturing defects) * In programmable circuits: missing devices due to permanent off crosspoints ** In programmable circuits: extra devices due to permanent on crosspoints
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Introduction NW-based logic circuits Fault models at device level Fault models at logic level Conclusions and challenges
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Hierarchical structure
Logic circuit made of devices made of NWs
Single faults
For each device in the structure
For each fault model at device level Analyse the fault propagation to the circuit’s output
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Introduction NW-based logic circuits Fault models at device level Fault models at logic level Conclusions and challenges
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Definition of fault models for nanowire-based
Bottom-up methodology
Physical Device Logic
The methodology can be applied to other
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Modelling a wider set of faults
Wearout faults Transient faults Multiple faults
Fault models for other nanodevices
CNT, molecular, spintronics, …
Dependability assessment of emerging (fault/defect
tolerant) nanoarchitectures
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