Course Summary for the Quiz ECE 65, Winter2013, F. Najmabadi - - PowerPoint PPT Presentation

Course Summary for the Quiz

ECE 65, Winter2013, F. Najmabadi

Devices

Diode iv characteristics equation

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (3/22)

IS : Reverse Saturation Current (10-9 to 10-18 A) VT : Volt-equivalent temperature (= 26 mV at room temperature) n: Emission coefficient (1 ≤ n ≤ 2 for Si ICs)

( )

1

/

− =

T D nV

v S D

e I i

: bias Reverse : bias Forward 3 | | For

/ S D nV v S D T D

I i e I i nV v

T D

− ≈ ≈ ≥

For derivation of diode iv equation, see Sedra & Smith Sec. 3

Sensitive to temperature:

• IS doubles for every 7oC increase
• VT = T(k) /11,600

Diode piecewise-linear model: Diode iv is approximated by two lines

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (4/22)

Constant Voltage Model

Si for V 7 . 6 . voltage, in"

• cut

" and : OFF Diode and : ON Diode − = < = ≥ =

D D D D D D D

V V v i i V v

Circuit Models: ON: OFF: Diode ON Diode OFF VD0

Zener Diode piecewise-linear model

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (5/22)

and : Zener and : OFF Diode and : ON Diode ≤ − = < < − = ≥ =

D Z D D D Z D D D D

i V v V v V i i V v

Diode ON Diode OFF VD0 Zener Circuit Models: ON: OFF: Zener:

Recipe for solving diode circuits

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (6/22)

Recipe:

• 1. Draw a circuit for each state of diode(s).
• 2. Solve each circuit with its corresponding diode equation.
• 3. Use the inequality for that diode state (“range of validity”) to

check

• if the solution is valid if circuit parameters are all known.
• to find the range of circuit “variable” which leads to that

state.

Accuracy of Constant-Voltage Model

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (7/22)

Constant Voltage Model

Diode ON Diode OFF VD0 Diode can be in forward bias with vD as small as 0.4 V when iD is small (Lab 4) In forward bias, “cut-in” voltage (VD0) can vary between 0.6 & 0.8 V (± 0.1 V) In forward bias, diode voltage changes slightly as current changes (discussed later in small signal model)

BJT iv characteristics includes four parameters

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (8/22)
• Two transistor parameters can be

written in terms of the other four:

• BJT iv characteristics equations are:

NPN transistor

CE BE BC B C E

v v v i i i − = + = : KVL : KCL Cut-off :

BE is reverse biased

Active:

BE is forward biased BC is reverse biased

(Deep) Saturation:

BE is forward biased BC is foward biased

, = =

C B

i i         + = = =

A CE V v S C V v S C B

V v e I i e I i i

T BE T BE

1

/ /

β β

B C sat CE V v S B

i i V v e I i

T BE

,

/

β β < ≈ = ) , ( ) (

CE B C BE B

v i g i v f i = =

Transistor operates like a “valve:” iC & vCE are controlled by iB

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (9/22)

Controller part: Circuit connected to BE sets iB Controlled part: iC & vCE are set by transistor state (&

• utside circuit)

BJT Linear Model

• Cut-off (iB = 0, vBE < VD0): Valve Closed

iC = 0,

• Active (iB > 0, vBE = VD0): Valve partially open iC = β iB, vCE > VD0
• Saturation (iB > 0 , vBE = VD0): Valve open

iC < β iB, vCE = Vsat

• For PNP transistor, replace vBE with vEB and replace vCE with vEC in the above.

V 2 . , V 7 . Si, For = =

sat D

V V * BJT Linear model is based on a diode “constant-voltage” model for the BE junction and ignores Early effect.

Recipe for solving BJT circuits

(State of BJT is unknown before solving the circuit)

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (10/22)
• 1. Write down BE-KVL and CE-KVL:
• 2. Assume BJT is OFF, Use BE-KVL to check:

a. BJT OFF: Set iC = 0, use CE-KVL to find vCE (Done!) b. BJT ON: Compute iB 3. Assume BJT in active. Set iC = β iB . Use CE-KVL to find vCE . If vCE ≥ VD0 , Assumption Correct, otherwise in saturation:

4. BJT in Saturation. Set vCE = Vsat . Use CE-KVL to find iC . (Double-check iC < β iB ) NOTE:

• For circuits with RE , both BE-KVL & CE-KVL have to be solved

simultaneously.

MOS i-v Characteristics Equations

NMOS (VOV = vGS – Vtn)

• For PMOS set VOV = vSG – |Vtp| & replace vDS with vSD in the above
• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (11/22)

[ ]

[ ]

DS OV

• x

n D OV DS OV DS DS OV

• x

n D OV DS OV D OV

v V L W C i V v V v v V L W C i V v V i V λ µ µ + = ≥ ≥ − = ≤ ≥ = ≤ 1 5 . and : Saturation 2 5 . and : Triode : Off

• Cut

2 2

PMOS NMOS

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (12/22)

Controller part: Circuit connected to GS sets vGS (or VOV ) Controlled part: iD & vDS are set by transistor state (&

• utside circuit)
• A similar solution method to BJT:
• Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve

with the corresponding MOS equation and validate the assumption.

• MOS circuits are simpler to solve because iG = 0 !
• However, we get a quadratic equation to solve if MOS in triode (check MOS in

saturation first!)

Functional Circuits

Rectifier & Clipper Circuits

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (14/22)

Half-wave rectifier

OFF) (Diode , For ON) (Diode , For = < − = ≥

• D

i D i

• D

i

v V v V v v V v

Clipper

OFF) Diode ( , For ON) Diode ( , For

i

• D

i D

• D

i

v v V v V v V v = < = ≥

“Clipping” voltage can be adjusted

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (15/22)

vo limited to ≤ VD0 + VZ vo limited to ≤ VD0 + VDC vo limited to ≥ − VD0 − VDC vo limited ≥ − VD0 −VZ

Both top & bottom portions of the signal can be clipped simultaneously

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (16/22)

vo limited to ≤ VD0 + VDC1 and ≥ − VD0 − VDC2 vo limited to ≤ VD0 + VZ1 and ≥ − VD0 − VZ2

Peak Detector Circuit

Peak Detector & Clamp Circuits

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (17/22)

Clamp Circuit

vo is equal to vi but shifted “downward” by − (V + − VD0)

• “ideal” peak detector: τ/T → ∞
• “Good” peak detector: τ/T >> 1

vo shifted “downward”

Voltage shift in a clamp circuit can be adjusted!

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (18/22)

) (

D Z i

• V

V V v v − − − =

+

) (

D DC i

• V

V V v v − − − =

+

vo shifted “upward”

) (

D Z i

• V

V V v v − − + =

−

) (

D DC i

• V

V V v v − − + =

−

BJT as a switch

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (19/22)
• Use: Logic gate can turn loads ON (BJT in saturation) or OFF

(BJT in cut-off)

• ic is uniquely set by CE circuit (as vce = Vsat)
• RB is chosen such that BJT is in deep saturation with a wide

margin (e.g., iB = 0.2 ic /β)

*Lab 4 circuit Solved in Lecture notes (problems 12 & 13) Load is placed in collector circuit

BJT as a Digital Gate

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (20/22)
• Other variants: Diode-transistor logic (DTL) and transistor-transistor logic (TTL)
• BJT logic gates are not used anymore except for high-speed emitter-coupled

logic circuits because of

• Low speed (switching to saturation is quite slow).
• Large space and power requirements on ICs

RTL NOT gate (VL = Vsat , VH = VCC) Resistor-Transistor logic (RTL) RTL NOR gate* RTL NAND gate* *Solved in Lecture notes (problems 14 & 15)

NMOS Functional circuits

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (21/22)
• Similar to a BJTs in the active mode,

NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

• Transition from cut-off to triode can

be used to build NMOS switch circuits.

• Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

• We can also built NMOS logic gate

similar to a RTL. But there is are much better gates based on CMOS technology!

Complementary MOS (CMOS) is based on NMOS/PMOS pairs

• F. Najmabadi, ECE65, Winter 2013, Course Summary for Quiz (22/22)
• Maximum signal swing: Low State: 0, High State: VDD
• Independent of MOS device parameters!
• Zero “static” power dissipation (iD = 0 in each state).
• It uses the fact that if a MOS is ON and iD = 0
• nly if MOS is in triode and vDS = 0

CMOS Inverter CMOS NAND Gate