ECE65 Course Summary ECE 65, Winter2013, F. Najmabadi
Devices
Diode iv characteristics equation ( ) = − / v D nV 1 i I e T D S I S : Reverse Saturation Current (10 -9 to 10 -18 A) V T : Volt-equivalent temperature (= 26 mV at room temperature) n : Emission coefficient (1 ≤ n ≤ 2 for Si ICs) ≥ For | | 3 v nV D T ≈ / v nV Forward bias : i I e D T D S ≈ − Reverse bias : i I D S Sensitive to temperature: I S doubles for every 7 o C increase V T = T (k) /11,600 For derivation of diode iv equation, see Sedra & Smith Sec. 3 F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (3/40)
Diode piecewise-linear model: Diode iv is approximated by two lines Constant Voltage Model Diode ON Diode OFF V D0 Circuit Models: = ≥ Diode ON : and 0 ON: v V i 0 D D D = < Diode OFF : 0 and i v V 0 D D D = − " cut - in" voltage, 0 . 6 0 . 7 V for Si V D 0 OFF: F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (4/40)
Zener Diode piecewise-linear model = ≥ Diode ON : and 0 v V i D D 0 D = − < < Diode OFF : 0 and i V v V 0 D Z D D = − ≤ Zener : and 0 v V i D Z D Diode ON Circuit Models: Diode OFF ON: V D0 OFF: Zener Zener: F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (5/40)
Recipe for solving diode circuits Recipe: 1. Draw a circuit for each state of diode(s). 2. Solve each circuit with its corresponding diode equation. 3. Use the inequality for that diode state (“range of validity”) to check o if the solution is valid if circuit parameters are all known. o to find the range of circuit “variable” which leads to that state. F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (6/40)
Accuracy of Constant-Voltage Model Constant Voltage Model Diode ON In forward bias, diode voltage changes slightly as current changes (discussed later in small signal model) Diode OFF V D0 Diode can be in forward bias with v D as In forward bias, “cut -in” voltage ( V D0 ) small as 0.4 V when i D is small (Lab 4) can vary between 0.6 & 0.8 V ( ± 0.1 V) F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (7/40)
BJT iv characteristics includes four parameters NPN transistor Cut-off : = = 0 , 0 i i B C BE is reverse biased i I = = / v V C S i e BE T Active: β β B BE is forward biased + v BC is reverse biased Two transistor parameters can be = / v V CE 1 i I e BE T C S V written in terms of the other four: A = + KCL : i i i E C B I = − = / (Deep) Saturation: v V KVL : S v v v i e BE T β BC BE CE B BE is forward biased BJT iv characteristics equations are: ≈ < β BC is foward biased , v V i i = CE sat C B ( ) i f v B BE = ( , ) i g i v C B CE F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (8/40)
Transistor operates like a “valve:” i C & v CE are controlled by i B Controlled part: i C & v CE are set by transistor state (& outside circuit) Controller part: Circuit connected to BE sets i B BJT Linear Model Cut-off ( i B = 0, v BE < V D 0 ): Valve Closed i C = 0, Active ( i B > 0, v BE = V D 0 ): Valve partially open i C = β i B, v CE > V D 0 Saturation ( i B > 0 , v BE = V D 0 ): Valve open i C < β i B, v CE = V sat For PNP transistor, replace v BE with v EB and replace v CE with v EC in the above. = = For Si, 0 . 7 V , 0 . 2 V V V 0 D sat * BJT Linear model is based on a diode “constant-voltage” model for the BE junction and ignores Early effect. F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (9/40)
Recipe for solving BJT circuits (State of BJT is unknown before solving the circuit) 1. Write down BE-KVL and CE-KVL: 2. Assume BJT is OFF, Use BE-KVL to check: BJT OFF: Set i C = 0, use CE-KVL to find v CE (Done!) a. BJT ON: Compute i B b. Assume BJT in active. Set i C = β i B . Use CE-KVL to find v CE . 3. If v CE ≥ V D 0 , Assumption Correct, otherwise in saturation: BJT in Saturation. Set v CE = V sat . Use CE-KVL to find i C . 4. (Double-check i C < β i B ) NOTE: o For circuits with R E , both BE-KVL & CE-KVL have to be solved simultaneously. F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (10/40)
MOS i-v Characteristics Equations NMOS PMOS NMOS ( V OV = v GS – V tn ) ≤ = Cut - Off : 0 0 V i OV D [ ] W ≥ ≤ = µ − 2 Triode : 0 and 0 . 5 2 V v V i C V v v OV DS OV D n ox OV DS DS L [ ] W ≥ ≥ = µ + λ 2 Saturation : 0 and 0 . 5 1 V v V i C V v OV DS OV D n ox OV DS L o For PMOS set V OV = v SG – | V tp | & replace v DS with v SD in the above F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (11/40)
MOS operation is “Conceptually” similar to a BJT -- i D & v DS are controlled by v GS Controlled part: i D & v DS are set by transistor state (& outside circuit) Controller part: Circuit connected to GS sets v GS (or V OV ) A similar solution method to BJT: o Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve with the corresponding MOS equation and validate the assumption. MOS circuits are simpler to solve because i G = 0 ! o However, we get a quadratic equation to solve if MOS in triode (check MOS in saturation first!) F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (12/40)
Foundation of Transistor Amplifiers MOS is always in saturation (BJT in active) Input to transistor is made of a constant bias part ( V GS ) and a signal ( v gs ): v GS = V GS + v gs Response ( v o = v DS ) is also made of a constant part ( V DS ) and a signal response part ( v ds ): v DS = V DS + v ds V DS , is ONLY related to V GS : o i.e., if v gs = 0 , then v ds = 0 The response to the signal is linear, i.e., v ds / v gs = const. But o v GS / v DS is NOT a constant! o V GS / V DS is NOT a constant! F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (13/40)
Issues in developing a transistor amplifier: 1. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias). o This will lead to different circuit configurations for bias versus signal 2. Compute circuit response to the signal o Focus on fundamental transistor amplifier configurations 3. How to establish a Bias point (bias is the state of the system when there is no signal). o Stable and robust bias point should be resilient to variations in µ n C ox (W/L),V t (or β for BJT) due to temperature and/or manufacturing variability. o Bias point details impact small signal response (e.g., gain of the amplifier). F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (14/40)
Summary of signal circuit elements Resistors& capacitors: The Same o Capacitor act as open circuit in the bias circuit. Independent voltage source (e.g., V DD ) : Effectively grounded Independent current source: Effectively open circuit Dependent sources: The Same Non-linear Elements: Different! o Diodes & transistors ? Diode Small Signal Model v D v d i D i d r d = nV T /I D F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (15/40)
Transistor Small Signal Models NMOS/PMOS NPN/PNP BJT ⋅ β 2 1 I V I V = ≈ = = = ≈ D g r T C A r g r λ ⋅ π m o m o V I I V r I π OV D B T C Comparison of MOS and BJT small-signal circuit models: 1. MOS has an infinite resistor in the input ( v gs ) while BJT has a finite resistor, r π (typically several k Ω ). 2. BJT g m is substantially larger than that of a MOS (BJT has a much higher gain). 3. r o values are typically similar (10s of k Ω). g m r o >> 1 for both. F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (16/40)
Transistor Biasing To make bias point independent of changes in transistor parameters (e.g. β ,) the bias circuit should “set” I C and NOT I B ! Emitter Degeneration (BJT): Current source: Requires a resistor in the emitter circuit. Requirements: << β + 1. ( 1 ) R R min B E ≥ 2. 1 V I E R E Source Degeneration (MOS): Requires a resistor in the source circuit. Requirement: > 1. R I V S D GS F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (17/40)
Emitter-degeneration bias circuits Basic Arrangement Bias with one power supply Bias with two power supplies (voltage divider) MOS source-degeneration bias circuits are identical To solve circuits with voltage divider bias: 1. BJT: replace voltage divider with its Thevenin equivalent. 2. MOS: Since i G = 0, calculate V G directly. F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (18/40)
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