[PPT] - ECE65 Course Summary ECE 65, Winter2013, F. Najmabadi Devices Diode PowerPoint Presentation

SLIDE 1

ECE65 Course Summary

ECE 65, Winter2013, F. Najmabadi

SLIDE 2

Devices

SLIDE 3

Diode iv characteristics equation

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (3/40)

IS : Reverse Saturation Current (10-9 to 10-18 A) VT : Volt-equivalent temperature (= 26 mV at room temperature) n: Emission coefficient (1 ≤ n ≤ 2 for Si ICs)

( )

1

/

− =

T D nV

v S D

e I i

: bias Reverse : bias Forward 3 | | For

/ S D nV v S D T D

I i e I i nV v

T D

− ≈ ≈ ≥

For derivation of diode iv equation, see Sedra & Smith Sec. 3

Sensitive to temperature:

IS doubles for every 7oC increase
VT = T(k) /11,600

SLIDE 4

Diode piecewise-linear model: Diode iv is approximated by two lines

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (4/40)

Constant Voltage Model

Si for V 7 . 6 . voltage, in"

cut

" and : OFF Diode and : ON Diode − = < = ≥ =

D D D D D D D

V V v i i V v

Circuit Models: ON: OFF: Diode ON Diode OFF VD0

SLIDE 5

Zener Diode piecewise-linear model

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (5/40)

and : Zener and : OFF Diode and : ON Diode ≤ − = < < − = ≥ =

D Z D D D Z D D D D

i V v V v V i i V v

Diode ON Diode OFF VD0 Zener Circuit Models: ON: OFF: Zener:

SLIDE 6

Recipe for solving diode circuits

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (6/40)

Recipe:

1. Draw a circuit for each state of diode(s).
2. Solve each circuit with its corresponding diode equation.
3. Use the inequality for that diode state (“range of validity”) to

check

if the solution is valid if circuit parameters are all known.
to find the range of circuit “variable” which leads to that

state.

SLIDE 7

Accuracy of Constant-Voltage Model

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (7/40)

Constant Voltage Model

Diode ON Diode OFF VD0 Diode can be in forward bias with vD as small as 0.4 V when iD is small (Lab 4) In forward bias, “cut-in” voltage (VD0) can vary between 0.6 & 0.8 V (± 0.1 V) In forward bias, diode voltage changes slightly as current changes (discussed later in small signal model)

SLIDE 8

BJT iv characteristics includes four parameters

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (8/40)
Two transistor parameters can be

written in terms of the other four:

BJT iv characteristics equations are:

NPN transistor

CE BE BC B C E

v v v i i i − = + = : KVL : KCL Cut-off :

BE is reverse biased

Active:

BE is forward biased BC is reverse biased

(Deep) Saturation:

BE is forward biased BC is foward biased

, = =

C B

i i         + = = =

A CE V v S C V v S C B

V v e I i e I i i

T BE T BE

1

/ /

β β

B C sat CE V v S B

i i V v e I i

T BE

,

/

β β < ≈ = ) , ( ) (

CE B C BE B

v i g i v f i = =

SLIDE 9

Transistor operates like a “valve:” iC & vCE are controlled by iB

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (9/40)

Controller part: Circuit connected to BE sets iB Controlled part: iC & vCE are set by transistor state (&

utside circuit)

BJT Linear Model

Cut-off (iB = 0, vBE < VD0): Valve Closed

iC = 0,

Active (iB > 0, vBE = VD0): Valve partially open iC = β iB, vCE > VD0
Saturation (iB > 0 , vBE = VD0): Valve open

iC < β iB, vCE = Vsat

For PNP transistor, replace vBE with vEB and replace vCE with vEC in the above.

V 2 . , V 7 . Si, For = =

sat D

V V * BJT Linear model is based on a diode “constant-voltage” model for the BE junction and ignores Early effect.

SLIDE 10

Recipe for solving BJT circuits

(State of BJT is unknown before solving the circuit)

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (10/40)
1. Write down BE-KVL and CE-KVL:
2. Assume BJT is OFF, Use BE-KVL to check:

a. BJT OFF: Set iC = 0, use CE-KVL to find vCE (Done!) b. BJT ON: Compute iB 3. Assume BJT in active. Set iC = β iB . Use CE-KVL to find vCE . If vCE ≥ VD0 , Assumption Correct, otherwise in saturation:

4. BJT in Saturation. Set vCE = Vsat . Use CE-KVL to find iC . (Double-check iC < β iB ) NOTE:

For circuits with RE , both BE-KVL & CE-KVL have to be solved

simultaneously.

SLIDE 11

MOS i-v Characteristics Equations

NMOS (VOV = vGS – Vtn)

For PMOS set VOV = vSG – |Vtp| & replace vDS with vSD in the above
F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (11/40)

[ ]

DS OV

x

n D OV DS OV DS DS OV

x

n D OV DS OV D OV

v V L W C i V v V v v V L W C i V v V i V λ µ µ + = ≥ ≥ − = ≤ ≥ = ≤ 1 5 . and : Saturation 2 5 . and : Triode : Off

Cut

2 2

PMOS NMOS

SLIDE 12

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (12/40)

Controller part: Circuit connected to GS sets vGS (or VOV ) Controlled part: iD & vDS are set by transistor state (&

utside circuit)
A similar solution method to BJT:
Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve

with the corresponding MOS equation and validate the assumption.

MOS circuits are simpler to solve because iG = 0 !
However, we get a quadratic equation to solve if MOS in triode (check MOS in

saturation first!)

SLIDE 13

Foundation of Transistor Amplifiers

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (13/40)
MOS is always in saturation (BJT in active)
Input to transistor is made of a constant

bias part (VGS ) and a signal (vgs): vGS = VGS + vgs

Response (vo = vDS ) is also made of a

constant part (VDS ) and a signal response part (vds): vDS = VDS + vds

VDS , is ONLY related to VGS :
i.e., if vgs = 0, then vds = 0
The response to the signal is linear, i.e.,

vds / vgs = const. But

vGS / vDS is NOT a constant!
VGS / VDS is NOT a constant!

SLIDE 14

Issues in developing a transistor amplifier:

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (14/40)
1. Find the iv characteristics of the elements for the signal (which

can be different than their characteristics equation for bias).

This will lead to different circuit configurations for bias versus signal
2. Compute circuit response to the signal
Focus on fundamental transistor amplifier configurations
3. How to establish a Bias point (bias is the state of the system

when there is no signal).

Stable and robust bias point should be resilient to variations in

µnCox (W/L),Vt (or β for BJT) due to temperature and/or manufacturing variability.

Bias point details impact small signal response (e.g., gain of the

amplifier).

SLIDE 15

Summary of signal circuit elements

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (15/40)
Resistors& capacitors: The Same
Capacitor act as open circuit in the bias circuit.
Independent voltage source (e.g., VDD) : Effectively grounded
Independent current source: Effectively open circuit
Dependent sources: The Same
Non-linear Elements:

Different!

Diodes & transistors ?

Diode Small Signal Model

vd id rd = nVT/ID vD iD

SLIDE 16

Transistor Small Signal Models

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (16/40)

1 2

D

OV

D m

I r V I g ⋅ ≈ ⋅ = λ

Comparison of MOS and BJT small-signal circuit models:
1. MOS has an infinite resistor in the input (vgs) while BJT has a finite resistor, rπ

(typically several kΩ).

2. BJT gm is substantially larger than that of a MOS (BJT has a much higher gain).
3. ro values are typically similar (10s of kΩ). gm ro >> 1 for both.

NMOS/PMOS

C A

T

C m B T

I V r r V I g I V r ≈ = = =

π π

β NPN/PNP BJT

SLIDE 17

Transistor Biasing

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (17/40)
To make bias point independent of changes in transistor

parameters (e.g. β,) the bias circuit should “set” IC and NOT IB !

Emitter Degeneration (BJT):

Requires a resistor in the emitter circuit.
Requirements:

1. 2.

V 1 ≥

E ER

I ) 1 (

min E B

R R + << β

Current source: Source Degeneration (MOS):

Requires a resistor in the source circuit.
Requirement:

1.

GS D S

V I R >

SLIDE 18

Emitter-degeneration bias circuits

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (18/40)

Basic Arrangement Bias with one power supply (voltage divider) Bias with two power supplies

MOS source-degeneration bias circuits are identical
To solve circuits with voltage divider bias:
1. BJT: replace voltage divider with its Thevenin equivalent.
2. MOS: Since iG = 0, calculate VG directly.

SLIDE 19

BJT Current Mirrors are based on two identical transistor with vBE,ref = vBE1

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (19/40)

Identical BJTs

Qref is always in active since
Identical BJTs and vBE,ref = vBE1
BJTs will have the same iB and the

same iC (ignoring Early effect)

, , , D ref BE ref CE ref C

V V V i = = > β

C C B ref C ref

i i i i I 2 2 : KCL

,

+ = + = / 2 1 1

ref ref C

I I i I ≈ + = = β

For the current mirror to work, Q1

should be in active:

1 1 D EE C CE

V V V V ≥ + =

Since I1 = const. regardless of

VC1 , this is a current source!

SLIDE 20

MOS Current-Steering Circuit are based on two identical transistor with vov,ref = vov1

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (20/40)
Qref is always in saturation since
OV

OV ref OV GS GS ref GS t ref GS ref GS ref DS

V V V V V V V V V V = = = = − > =

1 , 1 , , , , 2 1 1 1 2 ,

) / ( 5 . ) / ( 5 .

OV

x

n D OV ref

x

n ref D ref

V L W C i I V L W C i I µ µ = = = =

( ) ( )ref

ref

L W L W I I / /

1 1 =

For the current steering circuit to

work, Q1 should be in saturation:

t GS OV DS

V V V V − = >

1

Identical MOS: Same µCox and Vt

Since I1 = const. regardless of

VD1 , this is a current source!

SLIDE 21

How to add signal to the bias

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (21/40)

Bias & Signal vGS = VGS + vgs Bias & Signal vDS = VDS + vds

1. Direct Coupling
Use bias with 2 voltage supplies
For the first stage, bias such that

VGS = 0

For follow-up stages, match bias

voltages between stages

Difficult biasing problem
Used in ICs
Amplifies “DC” signals!
2. Capacitive Coupling
Use a capacitor to separate bias

voltage from the signal.

Simplified biasing problem.
Used in discrete circuits
Only amplifies “AC” signals

SLIDE 22

Discrete CE and CS Amplifiers

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (22/40)

|| ) || || (

D
G

i L D

m

i

r

R R R R R R r g v v = = − =

i

sig

i i sig

v

v R R R v v × + = || || ) || || (

C
B

i L C

m

i

r

R R r R R R R r g v v = = − =

π

∞ → π r

SLIDE 23

Discrete CE and CS Amplifiers with RE / RS

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (23/40)

[ ]

) 1 ( || / ) || ( 1 ) || (

S m

D
G

i

L

D S m L D m i

R

g r R R R R r R R R g R R g v v + = = + + − =

i

sig

i i sig

v

v R R R v v × + =                 + + + =       + + + = + + + − =

sig B E E

C
L

C E E B i E

L

C E m L C m i

R

R R r R r R R r R R R R r R R r R r R R R g R R g v v || 1 || ] / ) || [( 1 || ) / 1 ]( / ) || [( 1 ) || (

π π π

β β

SLIDE 24

Discrete CB and CG Amplifiers

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (24/40)

i

sig

i i sig

v

v R R R v v × + =

{ }

)] || || ( 1 [ || 1 ) || ( || || ) || || (

sig E m

C
m

L C

E

i L C

m

i

R

R r g r R R r g R R r r R R R R r g v v

π π

+ =       + + = + =

{ }

)] || ( 1 [ || 1 ) || ( || ) || || (

sig S m

D
m

L D

S

i L D

m

i

R

R g r R R r g R R r R R R R r g v v + =       + + = + = ∞ → π r

SLIDE 25

Discrete CC and CD Amplifiers

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (25/40)

1 || ) || || ( 1 ) || || (

m S

G

i L S

m

L S

m

i

g

R R R R R R r g R R r g v v = = + =

i

sig

i i sig

v

v R R R v v × + =

[ ]

|| || || ) || || ( || ) || || ( 1 ) || || (

sig

B E

L

E

B

i L E

m

L E

m

i

r

R R r R R R R r r R R R R r g R R r g v v β β

π π

+ ≈ + = + =

SLIDE 26

Gain of a multi-stage amplifier

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (26/40)

Example: A 3-stage amplifier

2 , 3 , 1 , 2 , 1 , 1 , 1 , 3 , 1 ,

i
i
i
v

v v v v v v v v v × × = = ...

3 2 1

× × × × + =

v v v sig i i sig

A

A A R R R v v

But we need to know RL,1, RL,2, RL,3, … in order to find AM s.

2 , 1 , i

v

v =

3 , 2 , i

v

v =

3 ,

v

v =

1 , 1 , 1 , 1 ,

,

i i sig i i sig i sig i

R R R R R v v v v = + = =

3 ,

R

R =

3 2 1 3 , 3 , 2 , 2 , 1 , 1 , 1 , v v v i

i
i
i
A

A A v v v v v v v v × × = × × =

2 1 i

v

v =

3 2 i

v

v =

SLIDE 27

What are RL and Rsig for each stage?

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (27/40)

Amp Model for Stage j-1

1 , , −

=

j

j

sig

R R

1 , , +

=

j i j L

R R

RL for each stage is the input resistance of the following stage.
Rsig for each stage is the output resistance of the previous stage.

Amp Model for Stage j+1

SLIDE 28

Procedure for Solving multi-stage Amplifiers

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (28/40)

Gain & Ri:

1.Start from the load side (nth stage),

Find the gain Av,n = (vo/vi)n and Ri,n .

2.For (n-1)th stage, set RL,n-1 = Ri,n

Find the gain Av,n-1 = (vo/vi)n-1 and Ri ,n-1 .
3. Repeat until reaching to the first stage. Then,

Ro:

1. Start from the source side (1st stage). Find Ro,1 .
2. Go to the second stage. Set Rsig,2 = Ro,1 . Find Ro,2

3.Continue to the last stage (nth stage). Then, Ro = Ro,n

...

3 2 1 1 ,

× × × × + = =

v v v sig i i sig

i

i

A A A R R R v v R R

SLIDE 29

Cut-off frequency of a multi-stage amplifier

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (29/40)

Similar to a single-stage amplifier, each capacitor introduces a pole: 1) Coupling capacitor at the input: 2) Coupling capacitor at the output: 3) Coupling capacitor between stages j-1 and j 4) By-pass capacitors for stage j (if exists) 5) Then:

1 1

) ( 2 1

c sig i p

C R R f + = π

pass by pass by bypass p

C R f

− −

= 2 1

,

π

co L

po

C R R f ) ( 2 1 + = π

cj j

j

i pj

C R R f ) ( 2 1

1 , , −

+ = π ...

2 1

+ + ≈

p p p

f f f

SLIDE 30

Diode Functional Circuits

SLIDE 31

Rectifier & Clipper Circuits

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (31/40)

Half-wave rectifier

OFF) (Diode , For ON) (Diode , For = < − = ≥

D

i D i

D

i

v V v V v v V v

Clipper

OFF) Diode ( , For ON) Diode ( , For

i

D

i D

D

i

v v V v V v V v = < = ≥

SLIDE 32

“Clipping” voltage can be adjusted

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (32/40)

vo limited to ≤ VD0 + VZ vo limited to ≤ VD0 + VDC vo limited to ≥ − VD0 − VDC vo limited ≥ − VD0 −VZ

SLIDE 33

Both top & bottom portions of the signal can be clipped simultaneously

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (33/40)

vo limited to ≤ VD0 + VDC1 and ≥ − VD0 − VDC2 vo limited to ≤ VD0 + VZ1 and ≥ − VD0 − VZ2

SLIDE 34

Peak Detector Circuit

Peak Detector & Clamp Circuits

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (34/40)

Clamp Circuit

vo is equal to vi but shifted “downward” by − (V + − VD0)

“ideal” peak detector: τ/T → ∞
“Good” peak detector: τ/T >> 1

SLIDE 35

vo shifted “downward”

Voltage shift in a clamp circuit can be adjusted!

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (35/40)

) (

D Z i

V

V V v v − − − =

+

) (

D DC i

V

V V v v − − − =

+

vo shifted “upward”

) (

D Z i

V

V V v v − − + =

−

) (

D DC i

V

V V v v − − + =

−

SLIDE 36

BJT as a switch

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (36/40)
Use: Logic gate can turn loads ON (BJT in saturation) or OFF

(BJT in cut-off)

ic is uniquely set by CE circuit (as vce = Vsat)
RB is chosen such that BJT is in deep saturation with a wide

margin (e.g., iB = 0.2 ic /β)

*Lab 4 circuit Solved in Lecture notes (problems 12 & 13) Load is placed in collector circuit

SLIDE 37

BJT as a Digital Gate

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (37/40)
Other variants: Diode-transistor logic (DTL) and transistor-transistor logic (TTL)
BJT logic gates are not used anymore except for high-speed emitter-coupled

logic circuits because of

Low speed (switching to saturation is quite slow).
Large space and power requirements on ICs

RTL NOT gate (VL = Vsat , VH = VCC) Resistor-Transistor logic (RTL) RTL NOR gate* RTL NAND gate* *Solved in Lecture notes (problems 14 & 15)

SLIDE 38

NMOS Functional circuits

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (38/40)
Similar to a BJTs in the active mode,

NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

Transition from cut-off to triode can

be used to build NMOS switch circuits.

Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

We can also built NMOS logic gate

similar to a RTL. But there is are much better gates based on CMOS technology!

SLIDE 39

Complementary MOS (CMOS) is based on NMOS/PMOS pairs

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (39/40)
Maximum signal swing: Low State: 0, High State: VDD
Independent of MOS device parameters!
Zero “static” power dissipation (iD = 0 in each state).
It uses the fact that if a MOS is ON and iD = 0
nly if MOS is in triode and vDS = 0

CMOS Inverter CMOS NAND Gate

SLIDE 40

How to Solve Problems

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (40/40)
1. What is Known?

(comes from problem description.)

2. What is the aim?

(Indentify circuit parameters that has to be calculated.)

3. How to get there?

(use recipes!)

First, write down all equations that govern the

circuit.

Make sure that you have enough equations to

solve for the unknowns.

Make sure that you the solution will give you the

answer to the problem.

Only the, start solving the equations.