Designing a Single Cycle Datapath Computer Science 104 Alvin R. - PowerPoint PPT Presentation

Designing a Single Cycle Datapath Computer Science 104 Alvin R. Lebeck cps 104 1

Administrivia  Homework Due Friday March 2  Prof. Hilton no office hours this week  Reading Ch 4.  Review  Register File  Where are we with respect to the BIG picture?  The Steps of Designing a Processor  Datapath Design cps 104 2

What did you learn last time? cps 104 3

Register Cells on a bus Q Q Q Q D D D D D D D D latch latch latch latch OE OE OE OE E E E E IE IE IE IE Q Q Q Q One can “source” and “sink” from any cell on the bus by activating the right controls, IE--input enable, and OE--output enable. cps 104 4

3-Port Register Cell D ata-In Bus-C Bus-B Q Complement Q Q Bus-A OutB OutA D E nable • Stores one bit of a register • Can Read onto Bus-A & Bus-B and Write from Bus-C Simultaneously cps 104 5

3-Port Register File EC EA EB Bus-C Bus-B Q Bit-1 Q Bus-A Bus-C Bus-B Q Bit-0 Q Bus-A cps 104 6

Address Decode Circuit D ata-in Bus-C Bus-B Register address: 01 Q Q Bus-A OutB OutA DE nable A0 A1 EA B0 B1 EB C0 C1 EC cps 104 7

Register File (Four 4-bit Registers) Reg-3 Reg-2 Reg-0 Reg-1 A3 One-bit Cell One-bit Cell One-bit Cell One-bit Cell B3 C3 A2 One-bit Cell One-bit Cell One-bit Cell One-bit Cell B2 C2 A1 One-bit Cell One-bit Cell One-bit Cell One-bit Cell B1 C1 A0 B0 One-bit Cell One-bit Cell One-bit Cell One-bit Cell C0 A-En Add-A1 Add-A0 B -En Add-B 1 Add-B 0 C -En Add-C 1 Add-C 0 cps 104 8

Digital Logic Summary ° Given Boolean function, generate a circuit to “realize” the function. ° Constructed circuits that can add and subtract. ° The ALU: a circuit that can add, subtract, detect overflow, compare, and do bit-wise operations (AND, OR, NOT) ° Shifter ° Memory Elements: SR-Latch, D Latch, D Flip-Flop ° Tri-state drivers & Bus Communication vs. MUX ° Register Files ° Control Signals modify what the circuit does with inputs • ALU, Shift, Register Read/Write cps 104 9

What is Computer Architecture? • Coordination of levels of abstraction Application Software Operating System Interface Between Compiler Firmware HW and SW Instruction Set CPU Memory I/O system Architecture, Memory, I/O Digital Design Circuit Design Hardware • Under a set of rapidly changing technology Forces cps 104 10

The Big Picture: Where are We Now?  The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today’s Topic: Datapath Design cps 104 11

Datapath Design ° How do we build hardware to implement the MIPS instructions? ° Add, LW, SW, Beq, Jump cps 104 12

An Abstract View of the Implementation Clk PC Instruction Address Ideal Instruction Instruction Rd Rs Rt Imm Memory 5 5 5 16 A Data 32 Rw Ra Rb Address 32 Ideal 32 DataOut 32 32-bit ALU Data Registers Data In Memory B Clk Clk 32 cps 104 13

The MIPS Instruction Formats ° All MIPS instructions are 32 bits long. The three instruction formats: 31 26 21 16 11 6 0 op rs rt rd shamt funct • R-type 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 • I-type immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 • J-type op target address 6 bits 26 bits ° The different fields are: • op: operation of the instruction • rs, rt, rd: the source and destination register specifiers • shamt: shift amount • funct: selects the variant of the operation in the “op” field • address / immediate: address offset or immediate value • target address: target address of the jump instruction cps 104 14

The MIPS Subset (We can’t implement them all!) 31 26 21 16 11 6 0 ° ADD and subtract op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits • add rd, rs, rt • sub rd, rs, rt 31 26 21 16 0 op rs rt immediate ° OR Immediate: 6 bits 5 bits 5 bits 16 bits • ori rt, rs, imm16 ° LOAD and STORE • lw rt, rs, imm16 • sw rt, rs, imm16 ° BRANCH: • beq rs, rt, imm16 31 26 0 op target address ° JUMP: 6 bits 26 bits • j target cps 104 15

The Hardware “Program” Instruction How do I build the Fetch hardware to implement Instruction the MIPS Decode instructions and Operand their sequencing? Fetch Execute Result Store Next Instruction cps 104 16

Combinational Logic Elements (Basic Building Blocks) CarryIn ° Adder A 32 Adder Sum 32 B Carry 32 ° MUX Select A 32 MUX Y 32 B 32 OP ° ALU A 32 ALU Result 32 B Zero 32 cps 104 17

Storage Element: Register (Basic Building Block) Write Enable ° Register • Similar to the D Flip Flop except Data In Data Out - N-bit input and output N N - Write Enable input • Write Enable: Clk - negated (0): Data Out will not change - asserted (1): Data Out will become the same as Data In. cps 104 18

Storage Element: Register File RW RA RB Write Enable 5 5 5 ° Register File consists of 32 registers: busA • Two 32-bit output busses: busW 32 32 32-bit busA and busB 32 Registers busB Clk • One 32-bit input bus: busW 32 ° Register is selected by: • RA selects the register to put on busA • RB selects the register to put on busB • RW selects the register to be written via busW when Write Enable is 1 ° Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: - RA or RB valid => busA or busB valid after “access time.” cps 104 19

Storage Element: Idealized Memory Write Enable Address ° Memory (idealized) Data In DataOut • One input bus: Data In 32 32 • One output bus: Data Out Clk ° Memory word is selected by: • Write Enable = 0: Address selects the word to put on the Data Out bus • Write Enable = 1: Address selects the memory word to be written via the Data In bus ° Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: - Address valid => Data Out valid after “access time.” cps 104 20

An Abstract View of the Implementation Clk PC Instruction Address Ideal Instruction Instruction Rd Rs Rt Imm Memory 5 5 5 16 A Data 32 Rw Ra Rb Address 32 Ideal 32 DataOut 32 32-bit ALU Data Registers Data In Memory B Clk Clk 32 cps 104 21

Clocking Methodology Clk Setup Hold Setup Hold Don’t Care . . . . . . . . . . . .  All storage elements are clocked by the same clock edge  Cycle Time >= CLK-to-Q + Longest Delay Path + Setup + Clock Skew  Longest delay path = critical path cps 104 22

An Abstract View of the Critical Path ° Register file and ideal memory: • The CLK input is a factor ONLY during write operation • During read operation, behave as combinational logic: - Address valid => Output valid after “access time.” Clk PC Instruction Address Ideal Instruction Instruction Rd Rs Rt Imm Memory 5 5 5 16 Data 32 Rw Ra Rb Address 32 Ideal 32 DataOut 32 32-bit ALU Data Registers Data In Memory Clk Clk 32 cps 104 23

The Steps of Designing a Processor ° Instruction Set Architecture => Register Transfer Language ° Register Transfer Language => • Datapath components • Datapath interconnect ° Datapath components => Control signals ° Control signals => Control logic cps 104 24

Overview of the Instruction Fetch Unit ° The common Register Transfer Language (RTL) operations • Fetch the Instruction: mem[PC] • Update the program counter: - Sequential Code: PC <- PC + 4 - Branch and Jump: PC <- “something else” PC Clk Next Address Logic Address Instruction Word Instruction 32 Memory cps 104 25

RTL: The ADD Instruction ° add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The ADD operation • PC <- PC + 4 Calculate the next instruction’s address cps 104 26

RTL: The Load Instruction ° lw rt, rs, imm16 • mem[PC] Fetch the instruction from memory • Address <- R[rs] + SignExt(imm16) Calculate the memory address • R[rt] <- Mem[Address] Load the data into the register • PC <- PC + 4 Calculate the next instruction’s address cps 104 27

RTL: The ADD Instruction 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits ° add rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] + R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address cps 104 28

RTL: The Subtract Instruction 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits ° sub rd, rs, rt • mem[PC] Fetch the instruction from memory • R[rd] <- R[rs] - R[rt] The actual operation • PC <- PC + 4 Calculate the next instruction’s address cps 104 29

Datapath for Register-Register Operations ° R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt • Ra, Rb, and Rw comes from instruction’s rs, rt, and rd fields • ALUctr and RegWr: control logic after decoding the instruction fields: op and func 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb Result busW 32 32 32-bit ALU 32 Registers 32 Clk busB 32 cps 104 30