Design Verification Introduction Virendra Singh Associate - - PowerPoint PPT Presentation

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Design Verification Introduction Virendra Singh Associate - - PowerPoint PPT Presentation

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Design Verification Introduction Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail:

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Design Verification

Introduction

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

Testing & Verification of VLSI Circuits

Lecture 2

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Importance of Formal Verification

Simulation

 Can be applied in any design level  But quality of verification fully depends on Simulation Patterns

  • Corner cases may be missed
  • Random is just random and does not cover corner cases

Emulation

 Implement on FPGA or other programmable device – need lot of preparation  Still verification quality fully depends on Simulation Patterns – corner cases problem remains Famous bug: Pentium Floating point bug - $500 m

15 Jan 2013 EE-709@IITB

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Design Verification

Specification Implementation Simulation with Checkers/ drivers Automatic Implementation (Synthesis) Property checking Equivalence Checking Formal Specification Simulation Based Verification Correct-by Construction Formal Verification

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Simulation-Based Verification

Bug Bug Bug Bug Bug Bug Initial State Bug

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Simulation Vs Formal Verification

  • Simulation/emulation
  • Formal Verification
  • Cannot cover all cases
  • Corner cases may be missed
  • Essential method and good for

initially debugging  Equivalent to all case simulation  No corner case w.r.t given property

15 Jan 2013 EE-709@IITB

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Simulation vs Formal Verification

  • Program testing can be used to show the

presence of the bugs, but never to show the absence! (E.W. Dijkstra)

15 Jan 2013 EE-709@IITB

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Simulation Vs Formal Verification

Example:

  • Exclusive-OR circuit
  • z = (~x & y) + (x & ~y)

15 Jan 2013 EE-709@IITB

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Simulation Vs Formal Verification

  • Transform the formulae for circuit to the one for

specification by mathematical reasoning z = ~b + ~c b = ~x + ~a c = ~a + ~y a = ~x + ~y z = ~b + ~c = ~(~x + ~a) + ~(~x + ~y) = a & x + a & y = (~x + ~y) & x + (~x + ~y )& y = x & ~y + ~x & y

  • All transformation are based on axioms and theorems
  • Mathematical proof of correctness of design

15 Jan 2013 EE-709@IITB

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Formal Verification

Techniques  Deductive Verification (Theorem proving)

  • Uses axioms, rules to prove system correctness
  • Difficult and time consuming

 Model Checking

  • Automatic technique to prove correctness of concurrent

systems

  • Symbolic algorithms (using BDD)

 Equivalence Checking

  • Check if two circuits are equivalent

15 Jan 2013 EE-709@IITB

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System level System level System level System level

SoC Verification

  • System-on-Chip (SOC) design
  • Increase of design complexity
  • Move to higher levels of abstraction

1E0 1E1 1E2 1E3 1E4 1E5 1E6 1E7

Number of components Level Gate RTL Algorithm Transistor Abstraction Accuracy

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System-on-Chip (SoC) design

  • Specification to architecture and down to

implementation

  • Behavior (functional) to structure

– System level: system specification to system architecture – RT/IS level: component behavior to component micro- architecture

Specification + constraints

Memory Memory µProcessor Interface Comp. IP Bus Interface Interface Interface Custom HW

System architecture + estimates

Processors IPs Memories Busses

RTL/IS Implementation + results

Registers ALUs/FUs Memories Gates Mem RF State

Control

ALU

Datapath

PC

Control Pipeline

State

IF FSM

State

IF FSM IP Netlist

RAM IR

Memory

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Bottlenecks in Design Cycles: Survey of 545 engineers by EETIMES 2000

Verification challenge

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System-level design & verification

Remove as many bugs as possible in the earlier stages Do not introduce new design errors when refining designs Formal verification in system-level designs: Property checking and equivalence checking ⇓

System-level RTL Transistor level

Bugs fix time Cost due to the delay/late time-to-market revenue loss

3 minutes delay 3 days delay 3 weeks delay

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Spec

Formal verification

  • “Prove” the correctness of designs

– Both design and spec must be represented with mathematical models – Mathematical reasoning – Equivalent to “all cases” simulations

  • Possible mathematical models

– Boolean function (Propositional logic)

  • How to represent and manipulate on computers

– First-order logic

  • Need to represent “high level” designs

– Higher-order logic

  • Theorem proving = Interactive method
  • Front-end is also very important

– Often, it determines the total performance of the tools

Mathematical models Design Front-end tool Verification engines

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Spec

Backgrounds Technology in Formal Verification

  • Methods for reasoning about

mathematical models

– Boolean function (Propositional logic)

  • SAT (Satisfiability checker)
  • BDD (Binary Decision Diagrams)

– First-order logic

  • Logic of uninterpreted functions

with equality – Higher-order logic

  • Theorem proving = Interactive

method

Mathematical models Design Front-end tool Verification engines

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Formal Equivalence Checking

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Formal Equivalence Checking

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Formal Equivalence Checking

  • Equivalence checking can be applied

at or across various levels

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CEC in Practice

Key observation: The circuit being verified usually have a number of internal equivalent functions

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Formal Equivalence Checking

a b c a b c f = ab + c F’ = (a+ c)(b+c)

a b c f

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Canonical Forms

15 Jan 2013 EE-709@IITB

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Formal Equivalence Checking

Complexity

  • Efficiency of the conversion to canonical

form

  • Memory requirement
  • Efficiency of the comparison of two

representation of the canonical form

  • Efficiency to generate the counter

example in case of a miscompare

15 Jan 2013 EE-709@IITB