Design Success: Foundry Perspective Jim Kupec CEO of AmmoCore - - PowerPoint PPT Presentation

2002 IEEE 3rd International Symposium on QUALITY ELECTRONIC DESIGN March 19-20, 2002 – San Jose, CA

Design Success: Foundry Perspective

Jim Kupec CEO of AmmoCore Technology, Inc. Previous President of UMC-USA

“It is not the strongest of the species to survive, nor the most intelligent, but rather the one most responsive to change.”

Charles Darwin, “On the Origin of the Species by Natural Selection”, 1859

Technology is Rapidly Advancing

0.18µm 0.13µm Cu 0.09µm Cu

SIA ROADMAP

* Courtesy of ITRS

UMC ROADMAP

1999 2000 2001 2002 2004 2003 2005 1999 2000 2001 2002 2004 2003 2005

0.18µm 0.13µm Cu 0.10µm Cu 0.07µm Cu * Courtesy of UMC

Technology is Rapidly Accelerating

Technology Node – DRAM Half-Pitch (nm) Year of Production

1995 1998 2004 2001 2007 2010 2013 2016

10 100 1000

ITRS Roadmap Acceleration Continues…Half Pitch

* Courtesy of ITRS

2001 DRAM ½ Pitch 2001 MPU/ASIC ½ Pitch

1999 ITRS DRAM Half- Pitch

2- year Node Cycle 3- year Node Cycle

Disintegration Allows More Advanced Resources But…

• Example

System

Specification

IC Design IP Sourcing Wafer

Fabrication

Assembly

and Test

…Coordination is Critical

The Big Hard Chips

Usable Gates in Different Technologies and Die Sizes

1 10 100 180nm 130nm 100nm 70nm Technologies Usable Gates in Millions

8 x 8mm 10x10mm 14x14mm 12x12mm

Big Chips are Real

20 x 20 mm

* Chip courtesy of Xilinx

The Big Hard Chip

Usable Gates in Different Technologies and Die Sizes

1 10 100 180nm 130nm 100nm 70nm Technologies Usable Gates in Millions

8 x 8mm 10x10mm 14x14mm 12x12mm 20x20mm

* From ITRS/ AmmoCore Estimates

Chip Size Estimates

50%

40%

10%

Design Gap

• EDA Methodology
• DSM
• Complexity
• IP
• Memory
• Analogue
• Integration of Logic

12 x 12mm 8 x 8mm

Chip Dimensions

% = Silicon consumed by various chip sizes

Rapidly Expanding Design Gap

• New systems will need to take advantage of

advances in IC manufacturing technology

• Finer process geometries provide ability to

manufacture >30M gates on a single die

• Ability to implement large Systems in silicon will

decline due to physical design limitations Physical design methodologies will not scale Physical design methodologies will not scale

20 40 60 80 100 0.35mm 0.25mm 0.18mm 0.13mm

Million Gates

Process Capability IC Design Capability

1997 1999 2001 2003

IC Physical Size (cm2) 4.8 8.0 8.5 9.0 Area after Mem (cm2) 2.9 4.8 5.1 5.4 Auto-layout Tx (M) 23.0 67.2 81.6 129.6 Equivalent Gates (M) 5.8 16.8 20.4 32.4

Sources: SIA, Dataquest

9.0 32.4

Design Gap Creates Opportunity… If Early Adoption is Successful

Cumulative Profit

Sensitivity of Profits over Product Life

* From Accelerating Innovation

20%

Entitlement

20% Cost Increase 30% Market/ASP

Challenges of Big Multi-Million Gate Chips

Deep Submicron Effects Are Critical Physical Methodologies Do Not Scale Engineering Team Coordination Raises Overhead Factors IP Integration

DSM Challenges

Metal Modeling

• Coupling
• Antenna
• Electro Migration

* Courtesy of UMC

Modularized Technology

e-SRAM e-FLASH SiGe-BiCMOS RF Inductor

Top Metal W Mx-1 Mx Mx-1' IMD

MIM Capacitor DT HS, LL, MPU, LP Starting Material Bulk, EPI, SOI, etc. Multi-layer Interconnect

Devices Core I/O Analog Low Vt Zero Vt Resistor Varactor

Twin-well / Triple-well / well isolation Passivation, Fuse, RDL e-DRAM Trench cell

* Courtesy of UMC

Platform Technology

0.13um SOC Platform Low-k Dielectrics (k =2.7) 8 Layers Cu Interconnect Libraries

Memory Compilers RF Design Kits

Gold IP Catalog

ARM, DAC’s, ADC’s, Advanced I/O’s

EDA Partners

Technology Files: DRC, LVS, RC Extraction Logic Transistors

MPU High Speed (HS) Low Leakage (LL) Very Low Leakage (VLL)

Mixed Signal/RF CMOS

• Zero Vt, Low Vt, 2.5V I/O,

3.3V I/O transistors

• Spiral Cu Inductors, Metal-

I-Metal Caps, Poly Resistor

e-Memories

e-SRAM: 2.28um2 bit cell e-DRAM: 0.31um2 cell =Technology Features = Design Support Features

Silicon Shuttle

0.13um Prototyping

EDA: Challenges of Big Chips

(multi-million gates > 10M)

THEN NOW FUTURE

1M 10M 100M

Gates Productivity

Place & Route Extraction Global + Local Optimization Place & Route Extraction Global + Local Optimization

Pre-Place IPs Pre-Place IPs

Auto Auto Manual Manual 1M 10M 100M

Productivity

...

Top Level Design Planning Top Level Design Planning

Global Routing & Optimization Global Routing & Optimization

B3 B3 B4 B4 B2 B2 B1 B1

Top-level Routing & Verification Top-level Routing & Verification Platform based Partitioning & Placement Platform based Partitioning & Placement

PRL & P&R PRL & P&R ...

1M 10M 100M

Productivity

BLOCK/ TILE FLAT PLATFORM

Gates Gates

Block/Tile Based Platform based Flat

PRL & P&R PRL & P&R PRL & P&R PRL & P&R

Micro Architecture

SRAM: Challenges

First 256 Bit SRAM

• Handcrafted
• Fixed Size
• Technology Bound
• Extremely Optimized

* Courtesy of Fairchild, circa 1970

THEN NOW FUTURE

Compilation

• Auto-Compilation
• Various Sizes (smaller)
• Technology Sets
• Non-Optimized

(limited range, cells, footprint)

SRAM Future

• Large Sizes

– Redundancy – 1T, 2T Cells – MRAM Cells

• Bit Density Approach 50%

DRAM

• ASIC Process Compatible
• Tolerable Process Cost

DRAM: Challenges

Most Successful 16K DRAM

• Handcrafted
• Fixed Size
• Technology Bound
• Extremely Optimized

* Courtesy of Mostek, circa 1976

THEN NOW FUTURE

EDRAM

• Place Macro
• Limited Implementation
• 8M – 256 Mbit
• Process Complexity Adder
• Non-evolved IP

EDRAM Future

• Technology lags ASICS
• Process Cost Adder
• Package Solution

Competition

Summary

Design must be able to coordinate multiple IP sets

“ Trust but Verify ”

New EDA tools/ methodologies required to cope w/ large densities and DSM

“ Target Needs ”

Adaption opportunities are accelerating

“ Proverbial Inflection Point ”