Design Success: Foundry Perspective Jim Kupec CEO of AmmoCore - PowerPoint PPT Presentation

2002 IEEE 3 rd International Symposium on QUALITY ELECTRONIC DESIGN March 19-20, 2002 – San Jose, CA Design Success: Foundry Perspective Jim Kupec CEO of AmmoCore Technology, Inc. Previous President of UMC-USA

“It is not the strongest of the species to survive, nor the most intelligent, but rather the one most responsive to change.” Charles Darwin, “On the Origin of the Species by Natural Selection”, 1859

Technology is Rapidly Advancing SIA ROADMAP UMC ROADMAP 1999 2000 2001 2002 2003 2004 2005 1999 2000 2001 2002 2003 2004 2005 0.13µm 0.10µm 0.07µm 0.13µm 0.09µm 0.18µm 0.18µm Cu Cu Cu Cu Cu * Courtesy of UMC * Courtesy of ITRS

Technology is Rapidly Accelerating ITRS Roadmap Acceleration Continues…Half Pitch 1000 Technology Node – DRAM Half-Pitch (nm) 2001 DRAM ½ Pitch 2001 MPU/ASIC ½ Pitch 1999 ITRS DRAM Half- Pitch 100 2- year Node Cycle 3- year Node Cycle 10 1995 1998 2001 2004 2007 2010 2013 2016 Year of Production * Courtesy of ITRS

Disintegration Allows More Advanced Resources But … � System � Wafer � Assembly � IC Design � IP Sourcing Specification Fabrication and Test …Coordination is Critical � � Example � � �

The Big Hard Chips Usable Gates in Different Technologies and Die Sizes 100 Usable Gates in Millions 10 14x14mm 12x12mm 10x10mm 8 x 8mm 1 180nm 130nm 100nm 70nm Technologies

Big Chips are Real 20 x 20 mm * Chip courtesy of Xilinx

The Big Hard Chip Usable Gates in Different Technologies and Die Sizes 100 Usable Gates in Millions 20x20mm 10 14x14mm 12x12mm 10x10mm 8 x 8mm 1 180nm 130nm 100nm 70nm Technologies * From ITRS/ AmmoCore Estimates

Chip Size Estimates Design Gap 10% • EDA Methodology 12 x 12mm • DSM • Complexity 40% Chip • IP Dimensions • Memory 8 x 8mm • Analogue • Integration of Logic 50% % = Silicon consumed by various chip sizes

Rapidly Expanding Design Gap Million Gates 1997 1999 2001 2003 100 Process Capability IC Physical Size (cm 2 ) 9.0 4.8 8.0 8.5 9.0 Area after Mem (cm 2 ) 2.9 4.8 5.1 5.4 IC Design Capability Auto-layout Tx (M) 23.0 67.2 81.6 129.6 80 32.4 Equivalent Gates (M) 5.8 16.8 20.4 32.4 Sources: SIA, Dataquest 60 • New systems will need to take advantage of advances in IC manufacturing technology 40 • Finer process geometries provide ability to 20 manufacture >30M gates on a single die 0 • Ability to implement large Systems in silicon will 0.35mm 0.25mm 0.18mm 0.13mm decline due to physical design limitations Physical design methodologies will not scale Physical design methodologies will not scale

Design Gap Creates Opportunity… If Early Adoption is Successful Sensitivity of Profits over Product Life Cumulative Profit Entitlement 20% Cost Increase 30% Market/ASP 20% * From Accelerating Innovation

Challenges of Big Multi-Million Gate Chips � Deep Submicron Effects Are Critical � Physical Methodologies Do Not Scale � Engineering Team Coordination Raises Overhead Factors � IP Integration

DSM Challenges Metal Modeling • Coupling • Antenna • Electro Migration * Courtesy of UMC

Modularized Technology Passivation, Fuse, RDL Multi-layer Interconnect RF Inductor MIM Capacitor M x IMD W Top Metal M x-1 ' M x-1 Devices SiGe-BiCMOS HS, LL, MPU, LP e-FLASH e-SRAM Core I/O Analog Low Vt Zero Vt Resistor Varactor Twin-well / Triple-well / well isolation e-DRAM Trench cell DT Starting Material Bulk, EPI, SOI, etc. * Courtesy of UMC

Platform Technology Mixed Signal/RF CMOS e-Memories Logic Transistors -Zero Vt, Low Vt, 2.5V I/O, MPU e-SRAM: 2.28um 2 bit 3.3V I/O transistors High Speed (HS) cell -Spiral Cu Inductors, Metal- Low Leakage (LL) e-DRAM: 0.31um 2 cell I-Metal Caps, Poly Resistor Very Low Leakage (VLL) 0.13um SOC Platform Low-k Dielectrics (k =2.7) 8 Layers Cu Interconnect EDA Partners Libraries Technology Files: Memory Compilers Gold IP Catalog DRC, LVS, RC Extraction Silicon Shuttle RF Design Kits ARM, DAC’s, ADC’s, 0.13um Prototyping Advanced I/O’s =Technology Features = Design Support Features

EDA: Challenges of Big Chips (multi-million gates > 10M) THEN NOW FUTURE Platform based Platform based Pre-Place IPs Pre-Place IPs Top Level Design Planning Top Level Design Planning Partitioning & Placement Partitioning & Placement Micro Architecture Place & Route Place & Route ... Manual B1 Manual B1 PRL PRL PRL PRL ... PRL PRL B3 B3 B4 & & & B4 & & & Auto B2 B2 Auto Extraction P&R P&R P&R Extraction P&R P&R P&R Global + Local Global + Local Global Routing & Optimization Global Routing & Optimization Top-level Routing & Verification Top-level Routing & Verification Optimization Optimization FLAT BLOCK/ TILE PLATFORM Productivity Productivity Productivity Platform based Flat Block/Tile Based Gates Gates Gates 1M 10M 100M 1M 10M 100M 1M 10M 100M

SRAM: Challenges THEN NOW FUTURE SRAM Future • Large Sizes – Redundancy First 256 Bit SRAM Compilation – 1T, 2T Cells • Handcrafted • Auto-Compilation – MRAM Cells • Bit Density Approach 50% • Fixed Size • Various Sizes (smaller) DRAM • Technology Bound • Technology Sets • ASIC Process Compatible • Extremely Optimized • Non-Optimized • Tolerable Process Cost (limited range, cells, footprint) * Courtesy of Fairchild, circa 1970

DRAM: Challenges THEN NOW FUTURE Most Successful 16K DRAM EDRAM EDRAM Future • Handcrafted • Place Macro • Technology lags ASICS • Fixed Size • Limited Implementation • Process Cost Adder • Technology Bound • 8M – 256 Mbit • Package Solution • Extremely Optimized Competition • Process Complexity Adder • Non-evolved IP * Courtesy of Mostek, circa 1976

Summary � Design must be able to coordinate multiple IP sets � “ Trust but Verify ” � New EDA tools/ methodologies required to cope w/ large densities and DSM � “ Target Needs ” � Adaption opportunities are accelerating � “ Proverbial Inflection Point ”