Data Hazards Philipp Koehn 9 October 2019 Philipp Koehn Computer - - PowerPoint PPT Presentation

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Data Hazards Philipp Koehn 9 October 2019 Philipp Koehn Computer - - PowerPoint PPT Presentation

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Data Hazards Philipp Koehn 9 October 2019 Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019 Data Hazard 1 Definition: instruction waits on result from prior instruction Example add $s0, $t0, $t1 sub $t0, $s0,

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SLIDE 1

Data Hazards

Philipp Koehn 9 October 2019

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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1

Data Hazard

  • Definition:

instruction waits on result from prior instruction

  • Example

add $s0, $t0, $t1 sub $t0, $s0, $t3 – add instruction writes result to register $s0 in stage 5 – sub instruction reads $s0 in stage 2 ⇒ Stage 2 of sub has to be delayed

  • We overcome this in hardware

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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2

Graphical Representation

IF

add $s0,$t0,$t1

200 400 600 800 1000

ID MEM WB EX

  • IF: instruction fetch
  • ID: instruction decode
  • EX: execution
  • MEM: memory access
  • WB: write-back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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3

Add and Subtract

IF

add $s0,$t0,$t1

200 400 600 800 1000

ID MEM WB EX IF

sub $t0,$s0,$t3

ID MEM WB EX

  • Add wiring to circuit to directly connect
  • utput of ALU for next instruction

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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4

Load and Subtract

IF

lw $s0,20($t0)

200 400 600 800 1000

ID MEM WB EX IF

sub $t0,$s0,$t3

ID MEM WB EX

bubble bubble bubble bubble bubble

1200

  • Add wiring from memory lookup to ALU
  • Still 1 cycle unused:

"pipeline stall" or "bubble"

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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5

forwarding

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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6

Add and Subtract

  • Example

add $s0, $t0, $t1 sub $t0, $s0, $t3

  • Plan

IF

add $s0,$t0,$t1

200 400 600 800 1000

ID MEM WB EX IF

sub $t0,$s0,$t3

ID MEM WB EX

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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7

Add (Stage 1)

Instruction Memory ALU Add Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Data Memory Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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8

Subtract (Stage 1), Add (Stage 2)

Registers ALU Add Address Instruction Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Data Memory Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back Instruction Memory

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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9

Subtract (Stage 2), Add (Stage 3)

ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Data Memory Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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10

Subtract (Stage 3), Add (Stage 4)

Data Memory ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Data Hazard

Data Memory ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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12

Forwarding Data

Data Memory ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back Selector

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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13

Forwarding Unit

  • Forwarding Unit must

– detect if there is a data hazard – forward the right register values

  • Relevant information for decision

– identify of input registers used in instruction currently in EX (either first or second operand) – identity of output register used in instruction currently in MEM – value of output register used in instruction currently in MEM

  • Format of decision

– Register value – Control lines for selectors for input to ALU

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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14

Formal Names

  • Relevant information for decision

– EX.Rs and EX.Rt identify of input registers used in instruction currently in EX (either first or second operand) – MEM.Rd identity of output register used in instruction currently in MEM – MEM.RdValue value of output register used in instruction currently in MEM

  • Format of decision

– Forward.Rs and Forward.Rt Register value – Hazard.Rs and Hazard.Rt Control lines for selectors for input to ALU

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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15

Forwarding Logic

  • Logic in forwarding unit

if (MEM.Rd == EX.Rs) Forward.Rs = MEM.RdValue Hazard.Rs = 1 else Hazard.Rs = 0 if (MEM.Rd == EX.Rt) Forward.Rt = MEM.RdValue Hazard.Rt = 1 else Hazard.Rt = 0

  • Must also check if "RegisterWrite" for instruction in MEM stage
  • Relevant information must be passed through stages

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Forwarding Unit

ALU Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Zero Result Selector IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate Selector Forwarding Unit EX.Rs EX.Rt ForwardA MEM.RdValue MEM.Rd ForwardB HazardB HazardA Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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17

stalling

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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18

Load and Subtract

  • Example

load $s0, 20($t0) sub $t0, $s0, $t3

  • Plan

IF

lw $s0,20($t0)

200 400 600 800 1000

ID MEM WB EX IF

sub $t0,$s0,$t3

ID MEM WB EX

bubble bubble bubble bubble bubble

1200

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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19

Load (Stage 1)

Instruction Memory ALU Add Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Data Memory Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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20

Subtract (Stage 1), Load (Stage 2)

Registers ALU Add Instruction Memory Address Instruction Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Data Memory Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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21

Subtract (Stage 2), Load (Stage 3)

Registers ALU Add Instruction Memory Address Instruction Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Data Memory Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Subtract (Stage 3), Load (Stage 4)

Data Memory ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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23

Data Hazard

Data Memory ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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24

Data Hazard

  • Our example

load $s0, 20($t0) sub $t0, $s0, $t3

  • Worse than add/sub hazard

– we need operand value in $s0 – we have not even retrieved it at this stage

  • Stalling

– load instruction processing has to move to stage 5 – sub instruction processing has to stall

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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25

Stalling

  • Hazard condition between 2 instructions
  • Second instruction has to be delayed
  • Technical solution:

insert a "nop" operation ("no operation")

  • Resets program counter

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Load and Sub Processing

IF

lw $s0,20($t0)

200 400 600 800 1000 1200

  • Fetch of load instruction

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Load and Sub Processing

IF

lw $s0,20($t0)

200 400 600 800 1000 1200

ID IF

sub $t0,$s0,$t3

  • Fetch of sub instruction

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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28

Load and Sub Processing

IF IF

lw $s0,20($t0)

200 400 600 800 1000 1200

ID

sub $t0,$s0,$t3

EX ID

  • Next stage

– load: address calculation – sub: instruction decode

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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29

Load and Sub Processing

ID ID IF IF

lw $s0,20($t0)

200 400 600 800 1000 1200

sub $t0,$s0,$t3

EX

Hazard

  • Next stage

– load: address calculation – sub: instruction decode

  • Registers are known now → hazard detected

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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30

Load and Sub Processing

ID IF IF

lw $s0,20($t0)

200 400 600 800 1000 1200

sub $t0,$s0,$t3

EX

bubble

IF

X

  • Insertion of nop instruction

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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31

Load and Sub Processing

ID IF IF

lw $s0,20($t0)

200 400 600 800 1000 1200

sub $t0,$s0,$t3

EX

bubble

MEM

bubble

ID IF

X

  • Next stage

– load: memory retrieve – sub: instruction decode

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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32

Load and Sub Processing

ID IF IF

lw $s0,20($t0)

200 400 600 800 1000 1200

sub $t0,$s0,$t3

EX

bubble

MEM

bubble

ID WB EX

bubble

IF

X

  • Next stage

– load: write to register – sub: ALU operation execution

  • Operand for sub forwarded from load instruction execution

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Hazard Detection (Stalling) Unit

  • Stalling unit must

– detect if there is a data hazard – insert a "nop" instruction into pipeline

  • Relevant information for decision

– identify of input registers used in instruction currently in ID (either first or second operand) – identity of load register used in instruction currently in EX – control flag that there is indeed a memory read in EX

  • Format of decision

– overwrite instruction currently in ID with "nop" – reset program counter

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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34

Formal Names

  • Relevant information for decision

– ID.Rs and ID.Rt identify of input registers used in instruction currently in ID (either first or second operand) – EX.Rd identity of load register used in instruction currently in EX – EX.MemRead control flag that there is indeed a memory read in EX

  • Format of decision

– ID/EX

  • verwrite instruction currently in ID with "nop"

– PC reset program counter

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Stalling Logic

  • Logic in stalling unit

if (EX.MemRead and (EX.Rd = ID.Rs or EX.Rd = ID.Rt)) PC = PC - 4 ID/EX = nop

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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36

Stalling Unit

Registers Instruction Memory Address Instruction Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Selector PC IF: Instruction Fetch ID: Instruction decoder register file read Hazard Detection Unit ID.Rs ID.Rt EX.Rd ID/EX EX.MemRead Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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Additional Forwarding Logic

  • Additional logic in forwarding unit

if (WB.Rd == EX.Rs) Forward.Rs = WB.RdValue Hazard.Rs = 1 else Hazard.Rs = 0 if (WB.Rd == EX.Rt) Forward.Rt = WB.RdValue Hazard.Rt = 1 else Hazard.Rt = 0

  • Also relevant in "add, anything, add" sequence

where result from first add is used in last add

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019

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38

Forwarding Unit

Data Memory ALU Add Instruction Memory Address Instruction Registers Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Address Write data Zero ADD Result Selector Selector Sign extended Shift Left PC Selector 4 Read data IF: Instruction Fetch ID: Instruction decoder register file read MEM: Memory access EX: Execute / address calculate WB: Write Back Selector Forwarding Unit

Philipp Koehn Computer Systems Fundamentals: Data Hazards 9 October 2019