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CSCI341 Lecture 36, Pipelining & Hazards RECALL... RECALL... - - PowerPoint PPT Presentation
CSCI341 Lecture 36, Pipelining & Hazards RECALL... RECALL... - - PowerPoint PPT Presentation
CSCI341 Lecture 36, Pipelining & Hazards RECALL... RECALL... HAZARDS Data Hazards Control Hazards Dukes of Hazzard DATA HAZARD Hardware solution: Include forwarding paths in the machines datapath. Even though results have not
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RECALL... HAZARDS
- Data Hazards
- Control Hazards
Dukes of Hazzard
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DATA HAZARD
Hardware solution: Include forwarding paths in the machine’s datapath. Even though results have not yet reached the writeback stage, the needed information is forwarded from a pipeline register to the input of the ALU (for example).
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HAZARD “DETECTION”
- Control logic inspects instruction registers used by
neighboring stages.
- eg, “If EX/MEM’s Rd = ID/EX’s Rs and EX/MEM’s Rd = ID/
EX’s Rt”
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HAZARD
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FORWARDING
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“FORWARDING UNIT”
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DATA HAZARD
Can’t always solve this w/ hardware. For example: lw followed by add
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DATA HAZARD
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DATA HAZARD
One solution: Rearrange the assembly instructions so the instruction following a load is not one that uses the value fetched from memory. (Pipelined loads are often called “delayed loads.”)
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DATA HAZARD
What if the instructions can’t be rearranged? Then we insert a nop instruction. (“No Operation”)
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NOP
0000 0000 0000 0000 0000 0000 0000 0000 (sll $0, $0, 0)
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STALLING
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HAZARD DETECTION
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CONTROL HAZARDS
Associated with every branch/jump instruction.
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ONE SOLUTION
Assume the branch is not taken. (If it is, then we must flush the instructions that have already begun flowing through the pipeline.)
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AN IMPROVED SOLUTION
Determine the branch condition earlier (using additional logic circuitry.) The goal is to slightly reduce the number of “wasted” instructions (and cycles) that have entered the pipeline.
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DELAY SLOT
At the assembly level, organize the instructions such that the instruction immediately following a branch instruction is a useful one.
Loop: add $t0, $t0, $v0 addi $v0, $v0, -1 bnez $v0, Loop li $v0, 4 ... Loop: addi $v0, $v0, -1 bnez $v0, Loop add $t0, $t0, $v0 li $v0, 4 ...
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DYNAMIC BRANCH PREDICTION
In a nutshell: Keeping track of branch instruction histories, and consulting previous branch decisions to best predict the current one.
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EXCEPTIONS
aka “Interrupts” Important when considering pipelined architectures! I/O device request Invoke the OS Overflow HW Malfunction
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WHAT HAPPENS?
Save the address of the exceptional instruction (in the EPC, exception program counter). Transfer control to the OS at some specified address. OS can terminate the program or continue.
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OS EXCEPTION HANDLING
- What was the reason? (MIPS uses a “cause register”)
- Which instruction was the culprit? (EPC)
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EXCEPTIONS & PIPELINING
In essence, an exception is treated like a control hazard.
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NEXT....
Parallelism
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HOMEWORK
- Reading 30
- Project 8: “Flip