CS137: Today Electronic Design Automation Placement Problem - PDF document

CS137: Today Electronic Design Automation • Placement Problem • Partitioning � Placement • Quadrisection Day 16: November 9, 2005 • Refinement Placement (Intro, Constructive) 1 2 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Placement Bad Placement • Problem : Pick locations for all building • How bad can it be? blocks – Area – minimizing energy, delay, area – Delay – really: – Energy • minimize wire length • minimize channel density 3 4 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Bad: Area Bad: Delay • All critical path wires cross chip • All wires cross bisection • Delay =O(|PATH|*2*L side ) • O(N 2 ) area – [and L side as O(N)] • good: O(N) • good: O(|PATH|* L cell ) • compare 50ps gates to many nanoseconds to cross chip 5 6 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 1

Clock Cycle Radius Bad: Energy • Radius of logic can reach in one cycle (45 nm) • All wires cross chip: – Radius 10 O(L side ) long → O(L side ) capacitance per wire • Few hundred PEs • Recall Area � O(N 2 ) • So L side � O(N) – Chip side 600-700 PE × O(N) wires → O(N 2 ) capacitance • 400-500 thousand PEs – 100s of cycles to cross • Good: O(1) long wires → O(N) capacitance 7 8 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon “Closeness” Distance • Try placing “everything” close • Can we place everything close? 9 10 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Problem Characteristics • Familiar Constructive Placement – NP Complete – local, greedy not work – greedy gets stuck in local minima 11 12 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 2

Basic Idea Adequate? • Partition (bisect) to define halves of chip • Does recursive bisection capture the primary constraints of two-dimensional – minimize wire crossing placement? • Recurse to refine • When get down to single component, done 13 14 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Problems Interaction • Greedy, top-down cuts – maybe better pay cost early? • Two-dimensional problem – (often) no real cost difference between H and V cuts • Interaction between subtrees – not modeled by recursive bisect 15 16 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Example Interaction Ideal split “Equivalent” split (not typical) ignoring external constraints Practically -- makes all H cuts also be V cuts 17 18 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 3

Improvement: Ordered Problem • Order operations • Need to keep track of where things are • Keep track of existing solution – outside of current partition • Use to constrain or pass costs to next – include costs induced by above subproblem • Don’t necessarily know where things are – still solving problem A B 19 20 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Improvement: Ordered Improvement: Ordered • Order operations • Order operations • Keep track of existing solution • Keep track of existing solution • Use to constrain or pass costs to next • Use to constrain or pass costs to next subproblem subproblem • Flow cut • Flow cut S S – use existing in src/sink – use existing in src/sink – A nets = src, B nets = sink A A – A nets = src, B nets = sink • FM: start with fixed, unmovable nets for B side-biased inputs B T 21 T 22 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Improvement: Constrain Constrain Partition • Partition once • Constrain movement within existing partitions C A • Account for both H and V crossings • Partition next B – (simultaneously work parallel problems) D – easy modification to FM Solve AB and CD concurrently. 23 24 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 4

Improvement: Quadrisect Quadrisect • Solve more of problem at once • Modify FM to work on multiple buckets • Quadrisection: • k-way has: – partition into 4 bins simultaneously – k(k-1) buckets – |from| × |to| – keep track of costs all around – quad → 12 • reformulate gains • update still O(1) 25 26 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Quadrisect Recurse • Keep outside constraints • Cases (15): – (cost effects) – (1 partition) x 4 • Don’t know detail place – (2 part) x 6 = (4 choose 2) – (3 part) x 4 = (4 choose 3) • Model as at center of – (4 part) x 1 unrefined region 27 28 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Option: Terminal Propagation Option: Refine • Abstract inputs as • Keep refined terminals placement • Partition based upon • Use in cost estimates • Represent cost effects on placement/refinement decisions 29 30 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 5

Problem Iterate • After solve later problems • Still have ordering problem • Relax solution • Earlier subproblems solved with weak • Solve earlier problems constraints from later again with refined – (cruder placement estimates) placements (cost estimates) • Solved previous case by flattening • Repeat until converge – …but in extreme give up divide and conquer 31 32 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Iteration/Cycling Refinement • Relax using overlapping • General technique to deal with phase- windows ordering problem • Deal with edging effects – what order do we perform transformations, make decisions? – How get accurate information to everyone • Khang etc. claim 10- 15% improve • Still basically greedy – cycle – overlap 33 34 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Runtime Possible Refinement • Each gain update still O(1) • Allow unbalanced cuts – (bigger constants) – so, FM partition pass still O(N) – most things still work • O(1) iterations expected – just distort refinement groups • assume O(1) overlaps exploited – allowing unbalance using FM quadrisection looks a bit tricky • O(log(N)) levels – gives another 5-10% improvement • Total: O(N log(N)) – very fast compared to typical annealing • (annealing next time) 35 36 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 6

Uses Summary • Good by self • Partition to minimize cut size • Starting point for simulated annealing • Additional constraints to do well – speed convergence • With synthesis (both high level and logic) – Improving constant factors – get a quick estimate of physical effects • Quadrisection – (play role in estimation/refinement at larger level) • Early/fast placement • Keep track of estimated placement – before willing to spend time looking for best • Relax/iterate/Refine • For fast placement where time matters – FPGAs, online placement? 37 38 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon Big Ideas: Admin • Potential dominance of interconnect • ??? • Divide-and-conquer • Successive Refinement • Phase ordering: estimate/relax/iterate 39 40 CALTECH CS137 Fall2005 -- DeHon CALTECH CS137 Fall2005 -- DeHon 7