CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design - - PDF document
Synthesis and Place & Route Synopsys design compiler Cadence Encounter Digital Implementation System (EDI) CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural Verilog Cadence Your EDI Library
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# beh2str script set target_library [list [getenv "LIBFILE"]] set link_library [concat [concat "*" $target_library] $synthetic_library] read_file -f verilog [getenv "INFILE"] #/* This command will fix the problem of having */ #/* assign statements left in your structural file. */ set_fix_multiple_port_nets -all -buffer_constants compile -ungroup_all check_design #/* always do change_names before write... */ redirect change_names { change_names -rules verilog -hierarchy - verbose } write -f verilog -output [getenv "OUTFILE"] quit
set SynopsysInstall [getenv "SYNOPSYS"] set search_path [list . \ [format "%s%s" $SynopsysInstall /libraries/syn] \ [format "%s%s" $SynopsysInstall /dw/sim_ver] \ ] define_design_lib WORK -path ./WORK set synthetic_library [list dw_foundation.sldb] set synlib_wait_for_design_license [list "DesignWare-Foundation"] set link_library [concat [concat "*" $target_library] $synthetic_library] set symbol_library [list generic.sdb]
No clock defined so no target speed No wire load model, so fewer placement
No input drive defined so assume infinite drive No output load define so assume something
/uusoc/facility/cad_common/local/class/6710/F13/synopsys #/* search path should include directories with memory .db files */ #/* as well as the standard cells */ set search_path [list . \ [format "%s%s" SynopsysInstall /libraries/syn] \ [format "%s%s" SynopsysInstall /dw/sim_ver] \ !!your-library-path-goes-here!!] #/* target library list should include all target .db files */ set target_library [list !!your-library-name!!.db] #/* synthetic_library is set in .synopsys_dc.setup to be */ #/* the dw_foundation library. */ set link_library [concat [concat "*" $target_library] $synthetic_library]
#/* below are parameters that you will want to set for each design */ #/* list of all HDL files in the design */ set myFiles [list !!all-your-structural-Verilog-files!! ] set fileFormat verilog ;# verilog or VHDL set basename !!basename!! ;# Name of top-level module set myClk !!clk!! ;# The name of your clock set virtual 0 ;# 1 if virtual clock, 0 if real clock #/* compiler switches... */ set useUltra 1 ;# 1 for compile_ultra, 0 for compile # mapEffort, useUngroup are for # non-ultra compile... set mapEffort1 medium ;# First pass - low, medium, or high set mapEffort2 medium ;# second pass - low, medium, or high set useUngroup 1 ;# 0 if no flatten, 1 if flatten
#/* Timing and loading information */ set myPeriod_ns !!10!! ;# desired clock period (sets speed goal) set myInDelay_ns !!0.25!! ;# delay from clock to inputs valid set myOutDelay_ns !!0.25!! ;# delay from clock to output valid set myInputBuf !!INVX4!! ;# name of cell driving the inputs set myLoadLibrary !!Lib!! ;# name of library the cell comes from set myLoadPin !!A!! ;# pin that outputs drive #/* Control the writing of result files */ set runname struct ;# Name appended to output files
#/* the following control which output files you want. They */ #/* should be set to 1 if you want the file, 0 if not */ set write_v 1 ;# compiled structural Verilog file set write_ddc 0 ;# compiled file in ddc format set write_sdf 0 ;# sdf file for back-annotated timing sim set write_sdc 1 ;# sdc constraint file for place and route set write_rep 1 ;# report file from compilation set write_pow 0 ;# report file for power estimate
# analyze and elaborate the files analyze -format $fileFormat -lib WORK $myfiles elaborate $basename -lib WORK -update current_design $basename # The link command makes sure that all the required design # parts are linked together. # The uniquify command makes unique copies of replicated modules. link uniquify # now you can create clocks for the design if { $virtual == 0 } { create_clock -period $myPeriod_ns $myClk } else { create_clock -period $myPeriod_ns -name $myClk }
# Set the driving cell for all inputs except the clock # The clock has infinite drive by default. This is usually # what you want for synthesis because you will use other # tools (like SOC Encounter) to build the clock tree (or define it by hand). set_driving_cell -library $myLoadLibrary -lib_cell $myInputBuf \ [remove_from_collection [all_inputs] $myClk] # set the input and output delay relative to myclk set_input_delay $myInDelay_ns -clock $myClk \ [remove_from_collection [all_inputs] $myClk] set_output_delay $myOutDelay_ns -clock $myClk [all_outputs] # set the load of the circuit outputs in terms of the load # of the next cell that they will drive, also try to fix hold time issues set_load [load_of [format “%s%s%s%s%s” $myLoadLibrary \ "/" $myInputBuf "/" $myLoadPin]] [all_outputs] set_fix_hold $myClk
# now compile the design with given mapping effort # and do a second compile with incremental mapping # or use the compile_ultra meta-command if { $useUltra == 1 } { compile_ultra } else { if { $useUngroup == 1 } { compile -ungoup_all -map_effort $mapEffort1 compile -incremental_mapping -map_effort $mapEffort2 } else { compile -map_effort $mapEffort1 compile -incremental_mapping -map_effort $mapEffort2 } }
Set libraries in your own .synopsys_dc.setup analyze/elaborate define clock and set constraints compile write out results
use UofU_soc.conf as starting point. And Default.view
.../local/class/6710/F13/cadence/EDI
# global rda_Input # ######################################################### # Here are the parts you need to update for your design ######################################################### # # Your input is structural verilog. Set the top module name # and also give the .sdc file you used in synthesis for the # clock timing constraints. set rda_Input(ui_netlist) {!!filename!!.v} set rda_Input(ui_topcell) {!!TopCellName!!} set rda_Input(ui_timingcon_file) {!!filename!!.sdc}
# # Leave min and max empty if you have only one timing library # (space-separated if you have more than one) set rda_Input(ui_timelib) {!!filename!!.lib} set rda_Input(ui_timelib,min) {} set rda_Input(ui_timelib,max) {} # # # Set the name of your lef file or files # (space-separated if you have more than one). set rda_Input(ui_leffile) {!!filename!!.lef}
# Version:1.0 MMMC View Definition File # Do Not Remove Above Line create_rc_corner -name typical -preRoute_res {1.0} -preRoute_cap {1.0} - preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} - postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} - postRoute_clkcap {0.0} create_library_set -name 6710_typical -timing {!!your-lib-name.lib!!} create_constraint_mode -name typical -sdc_files {!!your-cell-name.sdc!!} create_delay_corner -name typical -library_set {6710_typical} -rc_corner {typical} create_analysis_view -name typical -constraint_mode {typical} -delay_corner {typical} set_analysis_view -setup {typical} -hold {typical}
And the other .tcl files it calls...
write another script to read in the floorplan and
############################################################# # You may not have to change things below this line - but check! # # You may want to do floorplanning by hand in which case you # have some modification to do! ############################################################# # Set some of the power and stripe parameters - you can change # these if you like - in particular check the stripe space (sspace) # and stripe offset (soffset)! set pwidth 9.9 ;# power rail width set pspace 1.8 ;# power rail space set swidth 4.8 ;# power stripe width set sspace 123 ;# power stripe spacing set soffset 120 ;# power stripe offset to first stripe set coregap 30.0 ;# gap between the core and the power rails
puts "-------------Floorplanning---------------" # # Make a floorplan - this works fine for projects that are all # standard cells and include no blocks that need hand placement... setDrawView fplan setFPlanRowSpacingAndType $rowgap 2 floorPlan -site core -r $aspect $usepct \ $coregap $coregap $coregap $coregap fit # # Save design so far saveDesign ${BASENAME}_fplan.enc saveFPlan ${BASENAME}.fp puts "--------------Floorplanning done----------
puts "-------------Power Planning----------------" puts "-------Making power rings------------------" # # Make power and ground rings - $pwidth microns wide # with $pspace spacing between them and centered in the channel addRing -spacing_bottom $pspace \
...
puts "------making power stripes-----------------” # Make Power Stripes. This step is optional. If you keep it # in remember to check the stripe spacing # (set-to-set-distance = $sspace) and stripe offset # (xleft-offset = $soffset)) addStripe -block_ring_top_layer_limit metal3 \
… # Use the special-router to route the vdd! and gnd! nets sroute -allowJogging 1 # Save the design so far saveDesign ${BASENAME}_pplan.enc puts "-------------Power Planning done---------"
If you have 1 or 2 in the geometry you might be
on-line tutorials for TCL Google “tcl tutorial” Synopsys documentation for design_compiler encounter.cmd (and documentation) for EDI
or BLOCK for later use...