Critical Power Slope: Understanding the Runtime Effects of - - PowerPoint PPT Presentation

Critical Power Slope:

Understanding the Runtime Effects of Frequency Scaling

Akihiko Miyoshi†,Charles Lefurgy‡, Eric Van Hensbergen ‡, Ram Rajamony ‡, Raj Rajkumar †

† Real-Time and Multimedia Systems Lab

• Dept. of Electrical and Computer Engineering

Carnegie Mellon University

‡Austin Research Laboratory

IBM

The Question

• Operating Points

– [600MHz,6V], [525MHz,4.2V],[450MHz,2.8V],[375MHz,2V],[300MHz, 1.7V], [225MHz,1.5V],[150MHz,1.45V]

• Where should I operate (for energy efficiency)?

– Dynamic Voltage Scaling (DVS) algorithms – Lowest performance without sacrificing user/application requirement

• Why lowest performance is not always the best

– Even for voltage scaling systems

Energy Efficiency

...

power time

active

E t

Watts

active

E

idle

E t

Watts

Low frequency High frequency

• Majority of OS policies assume
• Not always the case!

– When it is not the case? – How do we determine this?

Assumption

<

active

E t

Watts

active

E

idle

E t

Watts

• Motivation

– < : not always true – How do we choose which operating points to use?

• Measurement results
• Analytical model: Critical Power Slope
• Analysis on voltage scaling systems
• Conclusion

Outline

low

f

E

high

f

E

Power Management Techniques

• Provides multiple operating points

– [600MHz,6V],[450MHz,2.8V],[300MHz, 1.7V]…etc

• Three empirical data points

– Frequency Scaling

• PowerPC 405GP

– Clock Throttling

• Pentium with ACPI

– Voltage Scaling

• Strong ARM SA-1100
• Note: We are not making any statement on the

benefits of these techniques!

– These are merely samples which real systems use to manage power.

Basic Results

• Runtime and frequency

– CPU intensive workload: inverse relationship

• Power and frequency

– Frequency scaling, clock throttling processors

• CPU active: linear relationship
• CPU idle: constant

m: slope CPU active CPU idle

Power Frequency

Energy Consumption

• Compare energy consumption at different
• perating points

– Same workload W – Same amount of time t

active

E

idle

E t

power time

500 1000 1500 2000 2500 3000

12 25 37 50 62 75 87 100

CPU per f

• r

mance ( %)

Joul es Ext r a I dl e Syst em Act i ve

Energy consumption (Pentium L1 cache read hit)

2490J 2591J 174.3sec

Energy consumption (PPC L1 cache read hit)

50 100 150 200 66 133 200 266 M Hz Joul es Ex t r a I dl e Ot her s SDRAM CPU

136J 66.4sec 162J

Measurement Results

• Results consistent with different workloads

– Register, L1 cache, memory, disk accesses – Web server (Pentium)

• Pentium

– Highest frequency always energy efficient

• PowerPC

– Lowest frequency always energy efficient

• Why?

– What happens on voltage scaling systems?

• Motivation

– Which operating points should we consider?

• Measurement results

– Pentium: highest performance better – PowerPC: lowest performance better

• Analytical model: Critical Power Slope
• Analysis on voltage scaling systems
• Conclusion

Outline

• CPU intensive workload W
• Frequency

– Assume utilization of system = 1 – units of time to complete W – Energy consumed

• At frequency

– Time to compute W: – Remaining extra idle time:

Characterization

min

f

min f

T

min min min f f f

P T E =

) (

min

f f >

f f f

T

min min ) min 1 min( f f f

T

− idle f f f f f f f f

P T P T E ) 1 ( ) (

min min min min

− + =

– Power increases linearly with frequency – m: slope

• Is energy efficient??

– True if – Depends on m

Critical Power Slope

) (

min min

f f m P P

f f

− + =

idle f f f f f f f f

P T f f m P T E ) 1 ( )] ( )[ (

min min min min min min

− + − + =

min

f

min f f

E E >

• Use slope m to characterize system

– Find hypothetical m for and call it Critical Power Slope (CPS)

Critical Power Slope cont’d

min f f

E E =

min min

f P P critical

idle f

m

−

=

What does it mean?

Freq Power

critical

m

min

f

idle

P

min min

f P P critical

idle f

m

−

=

min f

P

idle

P

critical

m m <

critical

m m >

• If

– Energy efficient to run at higher freq. – Pentium

• If

– Energy efficient to run at lower freq. – PowerPC

Implications of CPS

critical

m m <

critical

m m >

028 . % 5 . 12 848 12 15 = × −

=

MHz W W critical

m

020 . % 5 . 12 848 15 30 = × −

=

MHz W W

m

0038 . 66 02 . 2 27 . 2 = −

=

MHz W W critical

m

0043 . 66 266 27 . 2 13 . 3 = − −

=

MHz MHz W W

m

min f f

E E >

min f f

E E >

<

J.Pouwelse, K.Langendoen, and H. Sips, “Dynamic Voltage Scaling on a Low-Power Microprocessor”, MOBICOM2001

Voltage Scaling Processors (Strong Arm SA-1100)

• Look at every operating point at frequency
• If

– Energy efficient at higher frequency than

• If

– Energy efficient at lower frequency than

CPS for voltage scaling system

x

f

fx P P

fx idle fx fx critical

m

−

=

fx critical fx

m m >

fx critical fx

m m <

x

f

x

f

Analysis on SA-1100

• Above 74MHz
• At 74MHz
• Below 74MHz
• Energy Inefficient below 74MHz!

001 . 74 46 121 74 = −

=

MHz mW mW MHz critical

m

001 . 59 74 106 121 74 = − −

=

MHz MHz mW mW MHz

m

fx critical fx

m m <

fx critical fx

m m >

Summary

Power Frequency Power Frequency Power Frequency Pentium PowerPC SA-1100

CPS: Characterizes the runtime trade-off of power management techniques

Conclusion

• Which operating points should we consider?

– Traditional DVS algorithms attempt to go to lowest frequency – Not always the best choice

• Critical Power Slope
• Identifies energy inefficient operating points
• Can be used to inform OS (DVS algorithms) of operating

points it should not consider