CPE 335 CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar - - PowerPoint PPT Presentation

CPE 335 CPE 335 Computer Organization MIPS ISA

• Dr. Iyad Jafar

Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/Courses/CPE335_S08/index.html

CPE 232 MIPS ISA 1

(vonNeumann) Processor Organization

• Control needs to

1.

input instructions from Memory

CPU Control Memory Devices Input

2.

issue signals to control the information flow between the Datapath components and to

Control Datapath Input Output

Datapath components and to control what operations they perform

Fetch

3.

control instruction sequencing

Decode Exec

Datapath needs to have the

components – the functional units and

storage (e.g., register file) needed to execute instructions

interconnects - components connected so that the instructions can

be accomplished and so that data can be loaded from and stored to Memory

CPE 232 MIPS ISA 2

y

Computer Language

• In order to command the computer, we must speak its

language, i.e. we must know its instructions and programming model (Instruction Set Architecture) model (Instruction Set Architecture)

• Computer instructions are represented as binary electric

signals at the hardware level Programming by storing signals at the hardware level. Programming by storing instructions in their binary format (Machine Language) is tedious and time consuming.

• Assembly language came into action and represented

machine codes/instructions as words. Assembling was done initially by hand Later assemblers were introduced initially by hand. Later, assemblers were introduced.

• In assembly, programmers have to write one line of code for

each instruction The programmers have to think like a each instruction. The programmers have to think like a machine.

• High-level programming languages and compilers

CPE 232 MIPS ISA 3

• High level programming languages and compilers

Computer Language

CPE 232 MIPS ISA 4

RISC - Reduced Instruction Set Computer

RISC philosophy

fixed instruction lengths load-store instruction sets limited addressing modes limited operations limited operations

MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, HP

(Compaq) Alpha (Compaq) Alpha, …

Instruction sets are measured by how well compilers

use them as opposed to how well assembly language use them as opposed to how well assembly language programmers use them Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memor space (embedded s stems)

CPE 232 MIPS ISA 5

memory space (embedded systems)

MIPS R3000 Instruction Set Architecture (ISA)

Instruction Categories

Computational

R0 R31 Registers

p

Load/Store Jump and Branch

R0 - R31

Floating Point

• coprocessor

Memory Management

PC HI

Memory Management Special

HI LO OP rs rt rd sa funct 3 Instruction Formats: all 32 bits wide R format OP OP rs rt immediate I format J format

CPE 232 MIPS ISA 6

OP jump target J format

Review: Unsigned Binary Representation

Hex Binary Decimal

0x00000000 0…0000 0x00000001 0…0001 1 0x00000002 0…0010 2 0x00000003 0011 3

31 30 29 . . . 3 2 1 0 bit position 231 230 229 . . . 23 22 21 20 bit weight

0x00000003 0…0011 3 0x00000004 0…0100 4 0x00000005 0…0101 5 1 1 1 . . . 1 1 1 1 bit 0x00000006 0…0110 6 0x00000007 0…0111 7 0x00000008 0…1000 8 1 0 0 0 . . . 0 0 0 0 - 1 0x00000008 0…1000 8 0x00000009 0…1001 9 … 232 - 1 0xFFFFFFFC 1…1100 0xFFFFFFFD 1…1101 0xFFFFFFFE 1…1110 232 - 2 232 - 3 232 - 4

CPE 232 MIPS ISA 7

0xFFFFFFFF 1…1111 232 - 1 2 2

Aside: Beyond Numbers

American Std Code for Info Interchange (ASCII): 8-bit

bytes representing characters

ASCII Ch ASCII Ch ASCII Ch ASCII Ch ASCII Ch ASCII Ch ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char

Null 32 space 48 64 @ 96 ` 112 p 1 33 ! 49 1 65 A 97 a 113 q 2 34 “ 50 2 66 B 98 b 114 r 2 34 50 2 66 B 98 b 114 r 3 35 # 51 3 67 C 99 c 115 s 4 EOT 36 $ 52 4 68 D 100 d 116 t 5 37 % 53 5 69 E 101 e 117 u 5 37 % 53 5 69 E 101 e 117 u 6 ACK 38 & 54 6 70 F 102 f 118 v 7 39 ‘ 55 7 71 G 103 g 119 w 8 bksp 40 ( 56 8 72 H 104 h 120 x 8 bksp 40 ( 56 8 72 H 104 h 120 x 9 tab 41 ) 57 9 73 I 105 i 121 y 10 LF 42 * 58 : 74 J 106 j 122 z 11 43 + 59 ; 75 K 107 k 123 { 11 43 + 59 ; 75 K 107 k 123 { 12 FF 44 , 60 < 76 L 108 l 124 | 15 47 / 63 ? 79 O 111

• 127

DEL

CPE 232 MIPS ISA 8

5 / 63 9 O

MIPS Register File

Register File Register File src1 addr

32 bits

src1

32 5

Holds thirty-two 32-bit registers

Two read ports and

src2 addr dst addr data

32 locations 5 5

One write port

ds add write data src2 data

32 32

Registers are

Faster than main memory

B t i t fil ith l ti

• But register files with more locations

are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) R d/ it t i i t d d ti ll write control

• Read/write port increase impacts speed quadratically

Easier for a compiler to use

• e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs.

e.g., (A B) (C D) (E F) can do multiplies in any order vs. stack

Can hold variables so that

d d it i ( i i t d ith f bit

CPE 232 MIPS ISA 9

• code density improves (since register are named with fewer bits

than a memory location)

Aside: MIPS Register Convention

Name Register Number Usage Preserve

• n call?

$zero constant 0 (hardware) n.a. $at 1 reserved for assembler n.a. $v0 - $v1 2-3 returned values no $a0 - $a3 4-7 arguments yes $t0 - $t7 8-15 temporaries no $s0 - $s7 16-23 saved values yes $t8 - $t9 24-25 temporaries no $gp 28 global pointer yes $sp 29 stack pointer yes $fp 30 frame pointer yes

CPE 232 MIPS ISA 10

$ra 31 return addr (hardware) yes

MIPS Arithmetic Instructions

MIPS assembly language arithmetic statement

add $t0, $s1, $s2 add $t0, $s1, $s2 sub $t0, $s1, $s2

Each arithmetic instruction performs only one

• peration

Each arithmetic instruction performs only one

• peration

Each arithmetic instruction fits in 32 bits and specifies

exactly three operands

Each arithmetic instruction fits in 32 bits and specifies

exactly three operands y p

destination ← source1 op source2

y p

destination ← source1 op source2

Operand order is fixed (destination first) Operand order is fixed (destination first) Those operands are all contained in the datapath’s

register file ($t0 $ 1 $ 2) indicated by $

CPE 232 MIPS ISA 11

register file ($t0,$s1,$s2) – indicated by $

Assembly Example 1

Given the following piece of C code, find the equivalent

assembly code using the basic MIPS ISA given so far. a = b – c d = 3 * a d = 3 a Solution: assume that the variables a, b, c, and d are associated with registers $s0 $s1 $s2 and $s3 associated with registers $s0, $s1, $s2, and $s3, respectively, by the compiler. b $ 0 $ 1 $ 2 # $ 0 t i b sub $s0, $s1, $s2 # $s0 contains b – c add $s3, $s0 ,$s0 # $s3 contains 2*a add $s3, $s3, $s0 # $s3 contains 3*a

CPE 232 MIPS ISA 12

Assembly Example 2

Given the following piece of C code, find the equivalent

assembly code using the basic MIPS ISA given so far. f = (g + h) – (i + j) Solution: assume that the variables f g h i and j are Solution: assume that the variables f, g, h, i, and j are associated with registers $s0, $s1, $s2, $s3, and $s4, respectively, by the compiler. add $t0, $s1, $s2 # $t0 contains g + h dd $t1 $ 3 $ 4 # $t1 t i i + j add $t1, $s3 ,$s4 # $t1 contains i + j sub $s0, $t0, $t1 # $s0 contains (g+h) – (i+j)

CPE 232 MIPS ISA 13

Machine Language - Add Instruction

Instructions are 32 bits long Arithmetic Instruction Format (R format): Arithmetic Instruction Format (R format):

add $t0, $s1, $s2

t d h t f t

• p rs rt rd

shamt funct

• p

6-bits

• pcode that specifies the operation

rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result’s destination shamt 5-bits shift amount (for shift instructions)

CPE 232 MIPS ISA 14

funct 6-bits function code augmenting the opcode

Machine language – Arithmetic Example

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Op code rs rt rd shamt funct Machine code for add $s0, $t0, $s0 in hexadecimal

0 0 $ 0 0 08 $ 0 0 10

• p = 0x0 rs = $t0 = 0x08 rt = $s0 = 0x10

rd = $s0 = 0x10 shamt = 0x00 funct = 0x20 M hi d f b $ 0 $t0 $ 0 i h d i l

000000 01000 10000 10000 00000 100000 Machine code for sub $s0, $t0, $s0 in hexadecimal

• p = 0x0 rs = $t0 = 0x08 rt = $s0 = 0x10

rd = $s0 = 0x10 shamt = 0x00 funct = 0x22

CPE 232 MIPS ISA 15

000000 01000 10000 10000 00000 100010

MIPS Logical Instructions

Similar to the arithmetic instructions, MIPS assembly

language supports some logical instructions.

and $s1, $s2, $s3 # $s1 = $s2 & $s3 bitwise

• r

$s1, $s2, $s3 # $s1 = $s2 | $s3 bitwise nor $s1, $s2, $s3

The instruction format is the R-type The instruction format is the R-type. 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Op code rs rt rd shamt funct Machine code for and $s1, $t2, $s2 in hexadecimal

• p

0 0 rs $t2 0 0A rt $s2 0 12

Op code rs rt rd shamt funct

• p = 0x0 rs = $t2 = 0x0A rt = $s2= 0x12

rd = $s1 = 0x11 shamt = 0x00 funct = 0x24

CPE 232 MIPS ISA 16

000000 01010 10010 10001 00000 100100

MIPS Memory Access Instructions

MIPS has two basic data transfer instructions for

accessing memory lw $t0, 4($s3) #load word from memory sw $t0 8($s3) #store word to memory sw $t0, 8($s3) #store word to memory

The data is loaded into (lw) or stored from (sw) a register

in the register file a 5 bit address in the register file – a 5 bit address

The memory address – a 32 bit address – is formed by

ddi th t t f th b dd i t (32 bit ) adding the contents of the base address register (32 bits) to the offset value (16 bits)

A 16-bit field meaning access is limited to memory locations A 16 bit field meaning access is limited to memory locations

within a region of ±213 or 8,192 words (±215 or 32,768 bytes) of the address in the base register

Note that the offset can be positive or negative

CPE 232 MIPS ISA 17

Note that the offset can be positive or negative

Machine Language - Load Instruction

Load/Store Instruction Format (I format):

lw $t0, 24($s2) lw $t0, 24($s2)

• p rs rt 16 bit offset

p Memory 0xf f f f f f f f

2410 + $s2 =

10

. . . 0001 1000

0x120040ac

$t0 $s2

0x12004094

+ . . . 1001 0100 . . . 1010 1100 = 0 120040

0x120040ac

$t0

0x00000004 0x00000008 0x0000000c

0x120040ac

CPE 232 MIPS ISA 18

data word address (hex) 0x00000000

Byte Addresses

Since 8-bit bytes are so useful, most architectures

address individual bytes in memory

The memory address of a word must be a multiple of 4

(alignment restriction)

Bi E di l ft t b t i d dd

Big Endian:

leftmost byte is word address

IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian:

rightmost byte is word address

Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msb lsb 3 2 1 0 little endian byte 0 msb lsb 0 1 2 3 big endian byte 0

CPE 232 MIPS ISA 19

Aside: Loading and Storing Bytes

MIPS provides special instructions to move bytes

lb $t0, 1($s3) #load byte from memory lb $t0, 1($s3) #load byte from memory sb $t0, 6($s3) #store byte to memory

6 bits 5 bits 5 bits 16 bits Opcode rs rt Offset What 8 bits get loaded and stored?

load byte places the byte from memory in the rightmost 8 bits of

the destination register

• what happens to the other bits in the register?
• what happens to the other bits in the register?

store byte takes the byte from the rightmost 8 bits of a register

and writes it to a byte in memory

CPE 232 MIPS ISA 20

• what happens to the other bits in the memory word?

Assembly Example 3

Assume that A is an array of 32-bit numbers whose base

address is stored in $s0. Convert the following C code into MIPS assembly language into MIPS assembly language. G = 2 * F A[17] = A[16] + G Solution: assume that the variables F and G are associated Solution: assume that the variables F and G are associated with registers $s4 and $s5, respectively.

dd $ 5 $ 4 $ 4 # $ 5 t i 2*F add $s5, $s4, $s4 # $s5 contains 2*F lw $t0, 64($s0) # $t0 contains A[16] (note the offset is 64) add $t0, $t0, $s5 # $t0 contains A[16] + G sw $t0, 68($s0) # store $t0 in A[17] (note the offset is 68)

CPE 232 MIPS ISA 21

sw $t0, 68($s0) # store $t0 in A[17] (note the offset is 68)

Machine language – Load/Store

6 bits 5 bits 5 bits 16 bits Opcode rs rt Offset Machine code for lw $s5, 4($s1) in hexadecimal

0 23 $ 1 0 11 $ 0 1

• p = 0x23 rs = $s1 = 0x11 rt = $s5 = 0x15
• ffset = 0x0004

M hi d f $ 0 16($ 4) i h d i l

100011 10001 10101 0000 0000 0000 0100 Machine code for sw $s0, 16($s4) in hexadecimal

• p = 0x2b rs = $s4 = 0x14 rt = $s0 = 0x10
• ffset = 0x0010

101011 10100 10000 0000 0000 0001 0000

CPE 232 MIPS ISA 22

101011 10100 10000 0000 0000 0001 0000

MIPS diti l b h i t ti

MIPS Control Flow Instructions

MIPS conditional branch instructions:

bne $s0, $s1, Lbl #go to Lbl if $s0≠$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1

Ex:

if (i j) h i + j;

Ex:

if (i==j) h = i + j; bne $s0, $s1, Lbl1 dd $ 3 $ 0 $ 1 add $s3, $s0, $s1 Lbl1: ...

Instruction Format (I format):

( )

6 bits 5 bits 5 bits 16 bits Opcode rs rt Offset beq opcode is 0x04 and bne opcode is 0x05 p

CPE 232 MIPS ISA 23

How is the branch destination address specified?

Specifying Branch Destinations

Use a register (like in lw and sw) added to the 16-bit offset

which register? Instruction Address Register (the PC)

it i t ti ll i li d b i t ti

• its use is automatically implied by instruction
• PC gets updated (PC+4) during the fetch cycle so that it holds the

address of the next instruction

limits the branch distance to -215 to +215-1 instructions from the

(instruction after the) branch instruction, but most branches are local anyway

ff t

16

from the low order 16 bits of the branch instruction

• ffset

00

sign-extend PC

Add 32 32 32 32 32

branch dst address

?

Add 4

CPE 232 MIPS ISA 24

32

?

4 32

Machine language – Control

6 bits 5 bits 5 bits 16 bits Opcode rs rt Offset Machine code for beq $s5, $s1, 20 in hexadecimal.

Assume that PC = 100.

• p = 0x04 rs = $s5 = 0x15 rt = $s1 = 0x11
• ffset = 0x0014

000100 10101 10001 0000 0000 0001 0100 Machine code for bne $s0, $s1, 13 in hexadecimal

• p = 0x05 rs = $s0 = 0x10 rt = $s1 = 0x11
• ffset = 0x000d

CPE 232 MIPS ISA 25

000101 10000 10001 0000 0000 0000 1101

More Branch Instructions

We have beq, bne, but what about other kinds of

brances (e.g., branch-if-less-than)? For this, we need yet another instruction lt another instruction, slt

Set on less than instruction:

slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1 else # $t0 # $t0 = 0

Instruction format (R format): 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Op code rs rt rd shamt funct Opcode for slt is 0x00 p

CPE 232 MIPS ISA 26

funct is 0x2a 2

More Branch Instructions, Con’t

Can use slt, beq, bne, and the fixed value of 0 in

register $zero to create other conditions

less than blt $ 1 $ 2 L b l

less than

blt $s1, $s2, Label slt $at, $s1, $s2 #$at set to 1 if b $ t $ L b l # $ 1 $ 2

less than or equal to

ble $s1, $s2, Label bne $at, $zero, Label # $s1 < $s2

greater than

bgt $s1, $s2, Label

great than or equal to

bge $s1, $s2, Label

Such branches are included in the instruction set as

d i t ti i d ( d d d) b th pseudo instructions - recognized (and expanded) by the assembler

Its why the assembler needs a reserved register ($at)

CPE 232 MIPS ISA 27

Its why the assembler needs a reserved register ($at)

MIPS l h diti l b h i t ti

Other Control Flow Instructions

MIPS also has an unconditional branch instruction or

jump instruction: j label #go to label

Instruction Format (J Format): Instruction Format (J Format): 6 bits 26 bits Opcode Address Field

26

from the low order 26 bits of the jump instruction

p

00

PC

4 32 00

CPE 232 MIPS ISA 28

Opcode is 0x02

PC

32

Aside: Branching Far Away

What if the branch destination is further away than can

be captured in 16 bits?

The assembler comes to the rescue – it inserts an The assembler comes to the rescue – it inserts an

unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1 becomes becomes bne $s0, $s1, L2 j L1 L2:

CPE 232 MIPS ISA 29

MIPS d ll i t ti

Instructions for Accessing Procedures

MIPS procedure call instruction:

jal ProcedureAddress #jump and link ja

• cedu e dd ess

#ju p a d

Saves PC+4 in register $ra to have a link to the next

instruction for the procedure return instruction for the procedure return

Machine format (J format): 6 bits 26 bits Opcode Address Field Then can do procedure return with a

jr $ra #return

Instruction format (R format): 6 bit 5 bit 5 bit 5 bit 5 bit 6 bit

CPE 232 MIPS ISA 30

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Op code rs

Aside: Spilling Registers

What if the callee needs more registers? What if the

procedure is recursive?

uses a stack – a last-in-first-out queue – in memory for passing

additional values or saving (recursive) return address(es)

One of the general registers,

$sp, is used to address the stack (which “grows” from high

high addr

stack (which grows from high address to low address)

add data onto the stack – push

high addr

add data onto the stack – push

$sp = $sp – 4 data on stack at new $sp

$sp top of stack

p

remove data from the stack – pop

data from stack at $sp

low addr

CPE 232 MIPS ISA 31

data from stack at $sp $sp = $sp + 4

MIPS Immediate Instructions

S ll t t d ft i t i l d

Small constants are used often in typical code Possible approaches?

put “typical constants” in memory and load them create hard-wired registers (like $zero) for constants like 1

addi $sp, $sp, 4 #$sp = $sp + 4

have special instructions that contain constants !

slti $t0, $s2, 15 #$t0 = 1 if $s2<15 M hi f t (I f t)

Machine format (I format): 6 bits 5 bits 5 bits 16 bits The constant is kept inside the instruction itself! Opcode rs rt Offset

CPE 232 MIPS ISA 32

The constant is kept inside the instruction itself!

Immediate format limits values to the range +215–1 to -215

Aside: How About Larger Constants?

We'd also like to be able to load a 32 bit constant into a

register, for this we must use two instructions

a new "load upper immediate" instruction

lui $t0 1010101010101010 lui $t0, 1010101010101010

16 0 8 1010101010101010 Then must get the lower order bits right, use

• ri $t0, $t0, 1010101010101010

1010101010101010 0000000000000000 0000000000000000 1010101010101010

CPE 232 MIPS ISA 33

1010101010101010 1010101010101010

MIPS Organization So Far

Processor Memory

1 1100

Register File

read/write 1…1100

src1 addr src2 addr dst addr src1 data 32 registers ($zero $ra) 32 5 5

230 words read/write addr

dst addr write data 32 bits src2 data ($zero - $ra) 32 32 32 5

read data

32 PC 32 32 Add 32 Add 32 32 branch offset

write data 0000 0…0100 0…1000 0…1100

32 ALU 32 1 2 3 7 6 5 4 Fetch PC = PC+4 D d E 32 32 4 32 bits

word address (binary) 0…0000

ALU 32 32 1 2 3 byte address (big Endian) Decode Exec

CPE 232 MIPS ISA 34

(big Endian)

Review of MIPS Operand Addressing Modes

Register addressing – operand is in a register

• p rs rt rd funct

Register

Base (displacement) addressing – operand is at the

l ti h dd i th f i t

word operand

memory location whose address is the sum of a register and a 16-bit constant contained within the instruction

• p

rs rt

• ffset

M

base register

• p rs rt offset

Memory

word or byte operand

Register relative (indirect) with 0($a0) Pseudo-direct with addr($zero)

base register Immediate addressing – operand is a 16-bit constant

contained within the instruction

CPE 232 MIPS ISA 35

• p rs rt operand

Review of MIPS Instruction Addressing Modes

PC-relative addressing –instruction address is the sum of

the PC and a 16-bit constant contained within the instruction instruction

• p rs rt offset

Memory

b h d ti ti i t ti Program Counter (PC) branch destination instruction Pseudo-direct addressing – instruction address is the 26-

bit constant contained within the instruction concatenated with the upper 4 bits of the PC with the upper 4 bits of the PC

• p jump address

Memory

jump destination instruction || Program Counter (PC) jump destination instruction ||

CPE 232 MIPS ISA 36

MIPS (RISC) Design Principles

Simplicity favors regularity

fixed size instructions – 32-bits small number of instruction formats

• pcode always the first 6 bits

Good design demands good compromises

three instruction formats

Smaller is faster

limited instruction set limited number of registers in register file limited number of addressing modes

Make the common case fast

arithmetic operands from the register file (load-store machine)

CPE 232 MIPS ISA 37

p g ( )

allow instructions to contain immediate operands

MIPS ISA So Far

Category Instr Op Code Example Meaning

Arithmetic (R & I add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3 subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3 (R & I format) add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6

• r immediate

13

• ri $s1, $s2, 6

$s1 = $s2 v 6 Data load word 35 lw $s1 24($s2) $s1 = Memory($s2+24) Data Transfer (I format) load word 35 lw $s1, 24($s2) $s1 Memory($s2+24) store word 43 sw $s1, 24($s2) Memory($s2+24) = $s1 load byte 32 lb $s1, 25($s2) $s1 = Memory($s2+25) store byte 40 sb $s1 25($s2) Memory($s2+25) $s1 store byte 40 sb $s1, 25($s2) Memory($s2+25) = $s1 load upper imm 15 lui $s1, 6 $s1 = 6 * 216 Cond. Branch br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L Branch (I & R format) br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L set on less than 0 and 42 slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0 t l th 10 lti $ 1 $ 2 6 if ($ 2 6) $ 1 1 l set on less than immediate 10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else $s1=0 Uncond. Jump jump 2 j 2500 go to 10000 j i t d 8 j $t1 t $t1

CPE 232 MIPS ISA 38

Jump (J & R format) jump register 0 and 8 jr $t1 go to $t1 jump and link 3 jal 2500 go to 10000; $ra=PC+4

MIPS ISA so far

Name Register Number Usage Preserve

• n call?

$zero constant 0 (hardware) n.a. $at 1 reserved for assembler n.a. $v0 - $v1 2-3 returned values no $a0 - $a3 4-7 arguments yes $t0 - $t7 8-15 temporaries no $s0 - $s7 16-23 saved values yes $t8 - $t9 24-25 temporaries no $gp 28 global pointer yes $sp 29 stack pointer yes $fp 30 frame pointer yes

CPE 232 MIPS ISA 39

$ra 31 return addr (hardware) yes

Examples on MIPS programming

Example 1: Convert the following high-level code into

MIPS assembly language. Make your own association for registers for registers. A = 5 ; B = 2 * A ; if B < array[12] then if B < array[12] then array[12] = 0 else array[12] = 5 array[12] = 5 end

CPE 232 MIPS ISA 40

Examples on MIPS programming

Example 2: Assume that the following assembly code is

loaded in the memory. Draw the memory and show its contents assuming that the program counter starts at contents assuming that the program counter starts at 0x00000400. add $s0, $s1, $s2 beq $s0, $s3, Next l $ 0 0($ 5) lw $s0, 0($s5) Next lw $s0, 0($s6)

CPE 232 MIPS ISA 41

Examples on MIPS programming

Example 3: what is the assembly language statements

corresponding to the following machine instructions

0x00af8020 0x0c001101

CPE 232 MIPS ISA 42

Examples on MIPS programming

Example 4: if the address of the following instructions is

0x00000008

What is the address of the instruction to be executed after the

following instruction g

j 256 j

What is the content of the $ra register after executing

jal 256

What is the address of the instruction if the condition checked by

the following instruction is true

CPE 232 MIPS ISA 43

beq $s1,$s2, 25

Examples on MIPS Programming

Example 5: compile the following function into MIPS

Assembly language. void strcpy (char x[], char y[]) { int i ; i = 0 ; hil (( [i] [i]) ! ‘\0’) while ((x[i] = y[i]) != ‘\0’) i += 1 ; }

CPE 232 MIPS ISA 44