Principles of Programming Languages - - PowerPoint PPT Presentation

Principles of Programming Languages

h"p://www.di.unipi.it/~andrea/Dida2ca/PLP-16/

• Prof. Andrea Corradini

Department of Computer Science, Pisa

• More on code genera;on

Lesson 14

2

Summary

• Next-use informa;on in basic blocks
• A Code Generator

– Register alloca;on and assignment

• Graph coloring

– Instruc;on selec;on

• Tree transducer
• An overview on Dataflow Analysis and some

Global Op;miza;on techniques

3

A Simple Code Generator

• Algorithm for genera;ng target code for a basic block

(sequence of three-address statements) using (local) next-use informa;on

• Cri;cal issue: how to use registers. Several compe;ng

uses:

– To store operands of a target code opera;on – Registers make good temporaries – To hold (global) values computed in a block and used in another (e.g., loop indexes) – To help run;me storage management (stack pointer, …)

• The algorithm will check if operands of three-address

code are available in registers to avoid unnecessary stores and loads.

4

(Local) Next-Use Informa;on

• Next-use informa0on is needed for dead-code

elimina;on and register assignment

• Next-use is computed by a backward scan of a basic

block and performing the following ac;ons on statement L: x := y op z

– Add liveness/next-use info on x, y, and z to statement L

• This info can be stored in the symbol table

– Before going up to the previous statement (scan up):

• Set x info to “not live” and “no next use”
• Set y and z info to “live” and the “next uses” of y and z to L

5

Next-Use (Step 1)

j: a := b + c k: t := a + b [ live(a) = true, live(b) = true, live(t) = true, nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ]

• Attach current live/next-use information (from symbol table)
• Since the is no info, assume variables are live
• [Data-flow analysis can provide accurate (global) information]

i: b := b + 1

6

Next-Use (Step 2)

j: a := b + c k: t := a + b [ live(a) = true, live(b) = true, live(t) = true, nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ] live(a) = true nextuse(a) = k live(b) = true nextuse(b) = k live(t) = false nextuse(t) = none

• Compute live/next-use informa;on at k and store in the symbol table

i: b := b + 1

7

Next-Use (Step 3)

j: a := b + c k: t := a + b [ live(a) = true, live(b) = true, live(t) = true, nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ]

• AZach current live/next-use informa;on from the symbol table to j

[ live(a) = true, live(b) = true, live(c) = true, nextuse(a) = k, nextuse(b) = k, nextuse(c) = none ] i: b := b + 1

8

Next-Use (Step 4)

j: a := b + c k: t := a + b live(a) = false nextuse(a) = none live(b) = true nextuse(b) = j live(c) = true nextuse(c) = j live(t) = false nextuse(t) = none [ live(a) = true, live(b) = true, live(t) = true, nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ] [ live(a) = true, live(b) = true, live(c) = true, nextuse(a) = k, nextuse(b) = k, nextuse(c) = none ]

• Compute live/next-use informa;on j

i: b := b + 1

9

Next-Use (Step 5)

j: a := b + c k: t := a + b [ live(a) = true, live(b) = true, live(t) = true, nextuse(a) = none, nextuse(b) = none, nextuse(t) = none ] [ live(a) = true, live(b) = true, live(c) = true, nextuse(a) = k, nextuse(b) = k, nextuse(c) = none ] i: b := b + 1 [ live(b) = true, nextuse(b) = j]

• AZach current live/next-use informa;on to i

10

Code Generator: assump;ons

• We assume that

– A set of register can be used for values used within the block – The order of statements in the block is fixed – Each three-address operator corresponds to a single machine instruc;on – Machine instruc;ons take operands in registers and leave the result in a register

• Allowed machine instruc;ons:

– LD reg, mem – ST mem, reg – OP reg, reg, reg

11

Code Generator: sketch

• For each three-address instruc;ons, the algorithm

– checks which operands are not in register, and emits corresponding loads – emits the opera;on – emits the store of the result, if needed

• The algorithm makes use of address descriptors and

register descriptors, and of func;on getreg() such that getreg(x = y OP z) returns the three registers to be used for x, y and z (denoted Rx, Ry and Rz).

12

Register and Address Descriptors

• For each available register, a register descriptor (RD)

keeps track of the vars whose current value in that register

– Ini;ally empty

• For each variable, an address descriptor (AD) keeps

track of the loca;ons where the current value of the var can be found

– Loca;on can be a register, a stack loca;on, a memory address, etc. – Can be stored in the symbol table

Managing Register and Address Descriptors

• For

LD R,x

– Change RD for R so it holds only x – Change AD for x by adding R as an addi;onal loca;on

• For

ST x,R

– Change AD for x to include its own memory loca;on

• For

OP Rx,Ry,Rz

– Change RD for Rx so it holds only x – Change AD for x so its only loca;on is Rx – Remove Rx from the AD of any variable other than x

13

The Code Genera;on Algorithm

• For a three-address instruc;on, e.g. x=y OP z

– Use getReg(x=y OP z) to select registers Rx, Ry, Rz for x, y, z – If y is not in Ry, emit an instruc;on LD Ry, y’ where y’ ∈ AD(y), preferably a register – Similarly for z – Issue the instruc;on OP Rx, Ry, Rz

• Copy statement x=y

– If y is not already in register, emit LD Ry, y’ – Adjust RD for Ry so it includes x – Change AD for x so its only loca;on is Ry

• Ending the basic block

– If x is used at other blocks, issue ST x, Rx

14

Example of code genera;on (1)

• t,u and v are temporaries, while a, b, c, d are

global variables

• Assume that registers are enaugh

– Reuse registers whenever possible

15

• t=a– b

u=a– c v=t+u a=d d

• d=v+u

Example of code genera;on (2)

• LDR1,a;LDR2,b;SUBR2,R1,R2

t=a b

a b c d

R1 R2 R3 v a b c d t u R1 R2 R3 v a b c d t u

• a

t a,R1 b c d R2

R1 R2 R3 v a b c d t u

LDR3,c;SUBR1,R1,R3 u=a c

u t c a b c,R3 d R2 R1

R1 R2 R3 v a b c d t u

• 16

Example of code genera;on (3)

• ADDR3,R2,R1

v=t+u

u t v a b c d R2 R1 R3

R1 R2 R3 v a b c d t u

• LDR2,d

a=d

u a,d v R2 b c d,R2 R1 R3

R1 R2 R3 v a b c d t u

• 17

Example of code genera;on (4)

18

• ADDR1,R3,R1

d=v+u

d a v R2 b c R1 R3

R1 R2 R3 v a b c d t u

• STa,R2;STd,R1

d a v a,R2 b c d,R1 R3

R1 R2 R3 v a b c d t u

19

The getreg algorithm

To compute getreg(x := y OP z)

1. If y is stored in a register R, return it as Ry 2. If y is not in a register, but exists R empty, return it as Ry 3. If y is not in a register and no register is empty, consider R and check any variable v ∈ RD(R) a. If AD(v) does not contain only R, OK. b. If v = x and x is not an operand in this instruc;on, OK. c. If v is not used later, then OK. d. Otherwise emit ST v,R this is a spill Choose R that minimizes the number of spills and return it as Ry 4. Same algorithm for determining Rz 5. For Rx, similar algorithm, but a. Any register containing x only is OK b. It is possible to return Ry for Rx if y is no more used and if RD(Ry) ={y}. Similarly for Rz.

To compute getreg(x := y)

1. Choose Ry as above 2. Choose Rx = Ry

20

Register Alloca;on and Assignment

• The code genera;on algorithm based on getreg() is not
• p;mal

– All live variables in registers are stored (flushed) at the end of a block: this could be not necessary

• Global register alloca3on assigns variables to limited

number of available registers and aZempts to keep these registers consistent across basic block boundaries

– Keeping variables in registers in looping code can result in big savings

• Groups of registers can be dedicated to certain values

(base addresses, arithme;cs, stack pointer)

– Simpler code generator, but less efficient use of registers

21

Alloca;ng Registers in Loops: Usage Counts

• Suppose

– not storing a variable x has a benefit of 2 – accessing a variable in register instead of in memory has benefit 1

• Let

– use(x, B) = number of uses of x in B before assignment – live(x, B) = 1 if x is assigned in B and live on exit from B

• Then the (approximate) benefit of alloca;ng a register

to a variable x within a loop L is ∑B∈L ( use(x, B) + 2 live(x, B) )

22

Global Register Alloca;on with Graph Coloring

• When a register is needed but all available registers

are in use, the content of one of the used registers must be stored (spilled) to free a register

• Graph coloring allocates registers and aZempts to

minimize the cost of spills

• Build a conflict graph (interference graph): two

variables have an edge if one is live where the other is defined

• Find a k-coloring for the graph, with k the number of

registers

23

Register Alloca;on with Graph Coloring: Example

a := read(); b := read(); c := read(); a := a + b + c; if (a < 10) { d := c + 8; write(c); } else if (a < 20) { e := 10; d := e + a; write(e); } else { f := 12; d := f + a; write(f); } write(d);

24

Register Alloca;on with Graph Coloring: Live Ranges

a := read(); b := read(); c := read(); a := a+b+c; a < 20 a < 10 d := c+8; write(c); f := 12; d := f+a; write(f); e := 10; d := e+a; write(e); write(d); a b c e f d d d

Live range

• f b

a f b d e c

Interference graph: connected vars have

• verlapping ranges

25

Register Alloca;on with Graph Coloring: Solu;on

a f b d e c

Interference graph

2 1 3 2 1 1

Solve Three registers: a = r2 b = r3 c = r1 d = r2 e = r1 f = r1

r2 := read(); r3 := read(); r1 := read(); r2 := r2 + r3 + r1; if (r2 < 10) { r2 := r1 + 8; write(r1); } else if (r2 < 20) { r1 := 10; r2 := r1 + r2; write(r1); } else { r1 := 12; r2 := r1 + r2; write(r1); } write(r2);

On Instruc;on Selec;on by Tree Rewri;ng

• Our simple algorithm uses a trivial Instruc;on Selec;on
• In prac;ce it is a difficult problem, mainly for CISC

machines with rich addressing mode

• Tree-rewri;ng rules can be used effec;vely for

specifying the transla;on from IR to target code

• Tree-transla;on schemes can be handled with

techniques similar to syntax-directed defini;ons: can be the basis of code-generator generators

• Start with a tree represen;ng the IR code, and reduce

it using the rules, producing the target code as associated ac;ons

26

• Code genera;on using a Tree Transla;on Scheme

Tree matching

• Various algorithms for paZern matching and general tree

matching

• LR parsing on a string (prefix) representa;on of trees

– Uses a syntax-directed transla;on scheme encoding the tree- transla;on scheme – Highly ambiguous. In absence of costs, reduce-reduce conflicts choose the longer reduc;on, shiO-reduce prefer shik

• General tree matching transforming templates into sets of

strings, and by matching mul;ple strings in parallel

• We can associate costs with the tree-rewri;ng rules and

apply dynamic programming to obtain an op;mal instruc;on selec;on

28

29

OptimalCodeGenerationfor Expressions

• Wecanchooseregistersoptimally

– Ifabasicblockconsistsofasingleexpression,or – Itissufficienttogeneratecodeforablcok one expression at a time expressionatatime

30

• Ershov Numbers
• Assignthenodesofanexpressiontreea

numberthattellshowmanyregistersneeded

– Labelleaf1 The label of an interior node with one child is the – Thelabelofaninteriornodewithonechildisthe labelofitschild – Thelabelofaninteriornodewithtwochildren

• thelargeroneifthelabelsaredifferent
• Oneplusthelabelifthelabelsarethesame

31

• Ershov Numbers

t2 t1 b e t3 t4 a

• t1=a– b

t2=c+d t3=e*t2 t4=t1+t3

d c

(ab)+e*(c+d)

32

• GeneratingCodeFromLabeled

ExpressionTree

• Recursivealgorithmstartingattheroot

– Labelkmeanskregisterswillbeused – Rb,Rb+1,…,Rb+k1 ,whereb>=1isabase

• Togeneratemachinecodeforanodewithlabelk

andtwochildrenwithequallabels

– Recursivelygeneratecodefortherightchild,using baseb+1:Rb+1,Rb+2,…,ResultinRb+k1 – Recursivelygeneratecodefortherightchild,using baseb:Rb,Rb+1,…,ResultinRb+k2 – GenerateinstructionOPRb+k1 ,Rb+k2 ,Rb+k1

• lek

33

• GeneratingCodeFromLabeled

ExpressionTree

• Togeneratemachinecodeforanodewith

labelkandtwochildrenwithunequallabels

– Recursivelygeneratecodeforthechildwithlabel k using base b: Rb Rb 1 Result in Rb k 1 k,usingbaseb:Rb,Rb+1,…,ResultinRb+k1 – Recursivelygeneratecodeforthechildwithlabel m,usingbaseb:Rb,Rb+1,…,ResultinRb+m1 – GenerateinstructionOPRb+k1 ,Rb+m1 ,Rb+k1

• Foraleafx,ifbaseisbgenerateLDRb,x

34

• Ershov Numbers

t2 t1 b e t3 t4 a

• LDR3,d

LDR2,c ADDR3,R2,R3 LDR2,e MULR3,R2,R3

d c

LDR2,b LDR1,a SUBR2,R1,R2 ADDR3,R2,R3

35

InsufficientSupplyofRegisters

• Input:alabeledtreeandanumberrofregisters
• ForanodeNwithatleastonechildlabeledror

greater

– recursivelygeneratecodeforthebigchildwithb=1. TheresultwillappearinRr – GeneratemachineinstructionSTtk,Rr – Ifthelittlechildhaslabelrorgreater,b=1.Ifthelabelis j<r,thenb=rj.TheresultinRr – GeneratetheinstructionLDRr1,tk – GenerateOPRr,Rr,Rr1 orOPRr,Rr1,Rr

36

• InsufficientSupplyofRegisters

t2 t1 b e t3 t4 a

Chapter8:CodeGeneration CS5810Spring2008 26

LDR2,d LDR1,c ADDR2,R1,R2 LDR1,e MULR2,R1,R2 STt3,R2

d c

LDR2,b LDR1,a SUBR2,R1,R2 LDR1,t3 ADDR2,R2,R1