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Core Switching and Routing Working Group Overview, Research Targets - - PowerPoint PPT Presentation

Core Switching and Routing Working Group Overview, Research Targets and Challenges Thierry E. Klein Chair, Core Switching and Routing Working Group GreenTouch Open Forum November 17 th , 2011 Overview Core Switching and Routing Working


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SLIDE 1

Core Switching and Routing Working Group

Overview, Research Targets and Challenges

Thierry E. Klein Chair, Core Switching and Routing Working Group GreenTouch Open Forum November 17th, 2011

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SLIDE 2

Overview

  • Core Switching and Routing Working Group
  • Technology Limitations
  • Energy Efficiency Challenges
  • Focus Statement
  • Membership
  • Energy Efficiency Improvement Opportunity
  • Research Targets
  • Key Research Projects and Activities
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SLIDE 3

Past and Anticipated Internet Growth

SKK, 2010 (Sources: RHK, 2004; McKinsey, JPMorgan, AT&T, 2001; MINTS, 2009; Arbor, 2009).

Internet Traffic Growth Rate YEAR 2000 2005 2010 2015 2020 2025 1995 ANNUAL GROWTH RATE (%) 250 200 150 100 50 300

RHK - NA McKinsey - NA MINTS - Global Arbor - Global

24-53%/year

Courtesy of Steve Korotky

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SLIDE 4

Traffic Growth and Technology Slow-Down

  • Traffic doubling every 2 years
  • 40% per year
  • 30x in 10 years
  • 1000x in 20 years
  • Slow-down in technology
  • Network energy efficiency

increasing 10-15% per year

  • Leading to an energy gap

0.001 0.01 0.1 1 10 100 1000 10000 1985 1990 1995 2000 2005 2010 2015 2020 Year Energy per bit Routed (nJ) IO (a-1) Logic (a-3) Constant Router Power (a-4) CMOS Feature size (a) x0.88/yr

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SLIDE 5

Some Specific Router Limitations

Buffer

Input Queuing Receive Fwd Engine Fabric Interface Output Fwd Engine Output Queuing L2 Buffering Optics Framer

Buffer Mem

L2 Buffering Optics Framer Switch Fabric Switch Fabric Switch Fabric Fabric Interface

L1+L2 L3 Switch 18 Chip-to-chip Interconnects

Buffer

Input Queuing Receive Fwd Engine Fabric Interface Output Fwd Engine Output Queuing L2 Buffering Optics Framer

Buffer Mem

L2 Buffering Optics Framer Switch Fabric Switch Fabric Switch Fabric Fabric Interface

L1+L2 L3 Switch 18 Chip-to-chip Interconnects Router T1600 (640Gb/s) 1,000 2,000 3,000 4,000 5,000 6,000 7,000 0% 20% 40% 60% 80% 100% Load W Router T1600 (640Gb/s) [From Kharitonov 2009]

D.Kharitonov, “Time-Domain Approach to Energy Efficiency: High-Performance Network Element Design” 2009 IEEE GLOBECOM Workshops

http://www.caida.org/research/traffic- analysis/pkt_size_distribution/graphs.xml

IPv4 Cumulative

INTERCONNECTS PACKET SIZE ENERGY DOES NOT FOLLOW LOAD

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SLIDE 6

Focus Statement for Core Switching and Routing

  • Network equipment hardware (routers

and switches)

  • Architecture and components
  • Functions, features and dimensioning
  • Low energy technologies (including

electronics, photonics, etc)

  • Power measurements
  • Network topologies and architectures
  • Tradeoff between optical and electronic data

transport

  • Optimal joint IP-optical network design
  • Packet versus circuit-switched architectures
  • Energy efficient and simplified routing
  • Integration of application and transport

layers

 Cross-layer optimization for efficient content distribution

  • Traffic engineering
  • Bandwidth allocation & traffic grooming
  • Elimination of over-provisioning
  • Efficient protection and restoration
  • Multicasting, elimination of junk and

redundant traffic ….

  • Network management, operation

and control

 Quality of service support  Network-wide reconfiguration and control of network elements (offline or

  • nline). Holistic, end to end approach

 Protocols and algorithms for managing and controlling network elements  Control and data plane  Energy and traffic monitoring

Focused on components, technologies, systems, algorithms and protocols at the data link layer (L2), the network layer (L3) and the transport layer (L4) as well as interactions with lower and higher layers and research efficiencies that can be obtained from cross-layer optimizations and joint designs

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SLIDE 7
  • Athens Information Technology

(AIT)

  • Bell Labs (Chair: Thierry Klein)
  • Broadcom
  • Chunghwa Telecom
  • Columbia University
  • Dublin City University
  • Electronics and

Telecommunication Research Institute (ETRI)

  • Energy Sciences Network /

Lawrence Berkeley Labs

  • Politecnico di Milano
  • Freescale Semiconductor
  • Fujitsu
  • Huawei Technologies
  • IBBT
  • IIIT Delhi
  • INRIA
  • KAIST
  • Karlsruhe Institute of Technology

28 members organizations with 67 individual members

  • Nippon Telegraph and Telephone

Corporation

  • Politecnico di Torino
  • Samsung Advanced Institute of

Technology (SAIT)

  • Seoul National University
  • University of Manchester
  • University of Melbourne
  • University College London
  • University of Cambridge
  • University of Leeds (Co-Chair:

Jaafar Elmirghani)

  • University of New South Wales
  • University of Toronto

Working Group Membership

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SLIDE 8

Energy Efficiency Improvement Opportunity

  • Provide assessment of potential opportunities for power efficiency

improvements in packet networks

  • Include the electronically switched portion of a service provider network,

including IP , Ethernet and OTN

  • Excluding fixed and wireless access networks
  • Excluding optical transport
  • Excluding opportunities for traffic reduction, e.g. via caching
  • Goal is to assess the opportunity for energy efficiency improvement

with a realistic path towards realization within the GreenTouch timeframe

  • Determine “independent” dimensions so that power efficiency

numbers can be multiplied to arrive at overall efficiency

  • pportunity
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SLIDE 9

Background and Assumptions

  • Timeframe:
  • Consistent with GreenTouch timeframe
  • Algorithms, architectures and technologies that can be demonstrated by

2015

  • With evolutionary improvements through 2020
  • Applied to 2020 traffic
  • Comparison with 2010 traffic and 2010 technologies
  • Assumptions:
  • Consider the traditional IP packet data network framework
  • Alternative paths and technologies are possible, but more speculative

and are not expected to fit in the timeframe:

  • Optical burst switching
  • Content centric networking
  • Adiabatic switching, quantum dot cellular automata, ….
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SLIDE 10

Overall Efficiency Opportunity

  • Defined 5 independent categories:
  • Chip level components and devices:

15x

  • Network element design:

1.5x

  • Network architecture:

2x

  • Dynamic resource management:

3x

  • Power utilization efficiency:

2x

  • Overall power efficiency opportunity:

270x

  • Caveats:
  • Numbers are best current estimates of efficiency improvement
  • pportunity
  • Large degree of uncertainty especially around network element

architecture and network architecture

  • Optimistic estimates since not clear if and how all the targets can be

achieved

  • Pessimistic estimates since constrained to current IP packet network

architectures and further-out technologies not considered

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SLIDE 11

Research Targets by Functional Topic (1)

Research Target Target Chip Level Components and Devices Low power electronics and photonics

3x – 10x

Opto-electronic integrated circuits

3x – 10x

Network Element Design Scalable and energy efficient router architectures for peta-bit routers

1.5x

Simplified and energy efficient protocols to eliminate unnecessary and redundant packet

  • processing. Energy efficient software

Integrated transceiver and wavelength circuit switching fabric operating in a core network to eliminate routing infrastructure and reduce layer-2 switch energy/bit for targeted services

10x

Network Architecture Network architectures, topologies and joint IP-optical design

3x – 10x

Energy efficient content routing (content router design, protocols and content placement and replacement algorithms)

10x

Energy optimized combined source and channel coding designed for end to end service dependent efficiency

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SLIDE 12

Research Targets by Functional Topic (2)

Research Target Target Dynamic Resource Management Rate adaptation and sleep cycles (processors, buffers, switch fabrics, linecards, router)

2x – 4x

Energy efficient routing

2x

Energy aware scheduling algorithms designed for delay tolerant services that enable end to end buffereless transmission respecting service QoS requirements Power aware protection and restoration

2x

Power Utilization Efficiency Passive cooling and advanced thermal management

1.5x

  • Requires equipment and network models with energy equations

to determine overall energy efficiency improvement opportunity

  • Gain understanding into which research targets are additive and

multiplicative

  • Gain understanding into most impactful research areas
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SLIDE 13

SCORPION Silicon Photonic Interconnects and Single- Chip Linecard

Contributing Members

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SLIDE 14

OPERA: OPtimal End to end Resource Allocation

Contributing Members

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SLIDE 15

STAR: SwiTching And tRansmission

Shuffle network Shuffle network 4x4 switch element 4x4 switch element Input shuffle network Output shuffle network Gating SOAs 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element 4x4 switch element

IP layer WDM layer

Contributing Members

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SLIDE 16

ZeBRA: Zero Buffer Router Architecture

Contributing Members

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SLIDE 17

REPTILE: Router Power Measurements

Contributing Members MODULAR SERVICES CARD

CP U Squ id GW

Egress Packet Flow From Fabric

RX METRO Ingres s Queui ng TX METR O From Fabric ASIC Egre ss Queu ing

4 7 6 5 2 3

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SLIDE 18

TIGER: TIme for a Greener Internet

1 3 2 5 4 7 6 9 8 11 10

Switch C

A B C

UTC Time is Used to Synchronize/Pipeline Forwarding of Time Frames

Switch A Switch B 3 TF Delay 4 TF Delay

TF TF TF TF

Time Frame containing a plurality of packets

Contributing Members

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SLIDE 19

SEASON Service Energy Aware Sustainable Optical Networks

Contributing Members

Energy & locality aware placement and execution of app center services Energy-aware wavelength routing & protocols

  • Univ. of Toronto

Columbia Univ.

INRIA

CEET Bell Labs

Multi-fiber, silicon-photonic fast switching & control devices End-to-end FEC Robust & distributed multi-layer control Service-aware flow switching

Enterprise

App Center

PoliMi Bell Labs UNSW

Bell Labs

  • Univ. of Toronto
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SLIDE 20

Research Targets and Mapping to Projects (1)

Research Target Projects Chip Level Components and Devices Low power electronics and photonics SCORPION, STAR Opto-electronic integrated circuits Network Element Design Scalable and energy efficient router architectures for peta-bit routers SCORPION Simplified and energy efficient protocols to eliminate unnecessary and redundant packet processing. Energy efficient software Integrated transceiver and wavelength circuit switching fabric operating in a core network to eliminate routing infrastructure and reduce layer-2 switch energy/bit for targeted services SEASON Network Architecture Network architectures, topologies and joint IP-optical design OPERA, TIGER, ZeBRA, STAR, SEASON Energy efficient content routing (content router design, protocols and content placement and replacement algorithms) CROCODILE (to be approved) Energy optimized combined source and channel coding designed for end to end service dependent efficiency SEASON

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SLIDE 21

Research Targets and Mapping to Projects (2)

Research Target Projects Dynamic Resource Management Rate adaptation and sleep cycles (processors, buffers, switch fabrics, linecards, router) OPERA, ZeBRA, REPTILE Energy efficient routing STAR, OPERA Energy aware scheduling algorithms designed for delay tolerant services that enable end to end buffereless transmission respecting service QoS requirements SEASON Power aware protection and restoration OPERA Power Utilization Efficiency Passive cooling and advanced thermal management