CompSci514/ECE558: Computer Networks Lecture 17: Programmable - - PowerPoint PPT Presentation

CompSci514/ECE558: Computer Networks

Lecture 17: Programmable Switches Xiaowei Yang xwy@cs.duke.edu http://www.cs.duke.edu/~xwy Some slides are adapted from Prof Nick McKeown’s lecture slides

Overview

• The Trio of modern networking

– SDN – NFV – Programmable switches

Network Functions Virtualisation

3

Software Defined Network (SDN)

Packet Forwarding Packet Forwarding Packet Forwarding Packet Forwarding Packet Forwarding Control Control Control Control Control

Global Network Map Control Plane Control Program Control Program Control Program

4

Motivation

• Network changes fast
• Need to extend the forwarding plane

History of Programmable Routers

• Mini-computer based routers (1969-1990)
• Active networks (Mid 1990)
• Software routers (1999 – present)

– Click, RouteBricks, PacketShader

• Software Defined Networking (2004– present)

Open Compute Project: Wedge switch

(open-source design from Facebook)

7

Switch chip! State of the art about 3.2Tb/s (32x100GE)

Linux

Feature Code

Control Plane

2014: The bare-metal switch

Feature Code Feature Code

Now I can tailor my network to meet my needs!

I can….

• 1. Quickly deploy new protocols.
• 2. See what my forwarding plane is doing.
• 3. Put expensive middlebox functions into the network.
• 4. Try out beautiful new ideas. Tailor my network to meet my

needs.

• 5. Differentiate. Now I own my intellectual property.

“Beautiful ideas”

• 1. Deploy new protocols and new headers
• 2. Simplify the data plane. Throw out unused protocols.
• 3. Reallocate resources in switches: tables, packet buffers, etc.
• 4. Add new telemetry for debugging and diagnostics
• 5. Verify network behavior
• 6. Embed “middlebox” functions into the network: load-balancing, gateways

and firewalls.

• 7. In-network congestion control
• 8. New routing and reliability algorithms
• 9. …

Linux

Feature Code

Control Plane

Driver

Tailoring my network switches today

Feature Code Feature Code New Feature Code

Can a CPU forward all my packets?

Packet Forwarding Speeds

0.1 1 10 100 1000 10000 100000 1990 1995 2000 2005 2010 2015 2020 Switch Chip

13

Gb/s

(per chip)

3.2Tb/s

Packet Forwarding Speeds

0.1 1 10 100 1000 10000 100000 1990 1995 2000 2005 2010 2015 2020 Switch Chip CPU

14

50x

Gb/s

(per chip)

3.2Tb/s

Conventional Wisdom: “Programmable devices are 10-100x slower. They consume much more power and area.”

Wedge

16

Whitebox CPU

Blackbox switch

My whitebox switch has a blackbox switch inside

Fixed-Function Switch Chips

Queues

L2

Stage

IPv4

Stage

Parser

IPv6

Stage

ACL

Stage

L3 L2 Packet Packet

18

Domain Specific Processors

GPU

Graphics

Compiler

Applications

DSP

Signal Processing

Compiler

Applications

My codec My renderer

Conventional wisdom said: programmability too expensive

Then, someone identified:

• 1. The right model for data-parallelism
• 2. Basic underlying processing primitives

Domain-specific processors were built Domain-specific languages, compilers and tool-chains

Control Flow Graph

Queues

L2

Stage

IPv4

Stage

Parser

IPv6

Stage

ACL

Stage

L2 Table IPv4 Table IPv6 Table ACL Table L2 v4 v6 ACL Control Flow Graph Switch Pipeline Fixed Action Fixed Action Action Fixed Action

21

Fixed-Function Switch Chips Are Limited

• 1. Can’t add new forwarding functionality

22

Fixed-Function Switch Chips

Queues

L2

Stage

IPv4

Stage

Parser

IPv6

Stage

ACL

Stage

L2 Table IPv4 Table IPv6 Table ACL Table Fixed Action Fixed Action Action Fixed Action L2 v4 v6 ACL Control Flow Graph Switch Pipeline MyEnca p MyEncap

23

24

Fixed-Function Switch Chips Are Limited

• 1. Can’t add new forwarding functionality
• 2. Can’t move resources between functions

Queues

L2

Stag e

IPv 4Sta

ge

Parser

IPv 6

Stag e

AC L

Stag e

Fixed Action Fixed Action Action L2 Table Fixed Action IPv4 Table IPv6 Table ACL Table

Control Flow Graph Switch Pipeline

Programmable Switch Chips

Queues

Parser Fixed Action Fixed Action Fixed Action L2 Table Fixed Action IPv4 Table IPv6 Table ACL Table Match Table Match Table Match Table Match Table L2 v4 v6 ACL Action Macro Action Macro Action Macro Action Macro

25

Match Table Action Macro

Mapping Control Flow to Programmable Switch Chip.

Queues

Parser Match Table Match Table Match Table L2 Table IPv4 Table IPv6 Table ACL Table Action Macro Action Macro Action Macro L2 v4 v6 ACL Control Flow Graph Switch Pipeline L2 v6 ACL v4 L2 Action Macro v4 Action Macro v6 Action ACL Action Macro

26

RMT: Reconfigurable Match + Action

(Now more commonly called “PISA”)

27

PISA: Protocol Independent Switch Architecture

28

Programmable Parser

Memory

Match+Action

ALU

Programmable Parser

Match+Action

P4 Programming

P4 code Compiler

Programmable Parser

Memory

Match+Action

ALU

Queues

Parser Fixed Action Fixed Action Fixed Action L2 Table Fixed Action IPv4 Table IPv6 Table ACL Table Match Table Match Table Match Table Match Table

P4 (http://p4.org/)

parser parse_ethernet { extract(ethernet); select(latest.etherType) { 0x800 : parse_ipv4; 0x86DD : parse_ipv6; } } table ipv4_lpm { reads { ipv4.dstAddr : lpm; } actions { set_next_hop; drop; } } control ingress { apply(l2_table); if (valid(ipv4)) { apply(ipv4_table); } if (valid(ipv6)) { apply(ipv6_table); } apply (acl); }

L 2 v4 v6

AC L

Action Macro Action Macro Action Macro Action Macro

31

Parser

Match Action Tables Control Flow Graph

Question

How can we exploit the parallelism within each stage?

32

Naïve Mapping: Control Flow Graph

Parser Match Table Match Table Match Table Match Table Action Macro Action Macro Action Macro Action Macro L2 v4 v6 ACL Control Flow Switch Pipeline

Queues

L2 Table IPv4 Table IPv6 Table ACL Table L2 v6 ACL v4 Action v4 Action Macro v6 Action Macro Action

33

Control Flow Graph L2

Table Dependency Graph (TDG)

v4 v6 ACL L2 v4 v6 ACL Table Dependency Graph

34

Switch Pipeline

Efficient Mapping: TDG

Queues

Parser L2 Table IPv4 Table IPv6 Table Table Dependency Graph Control Flow Graph L2 v4 v6 ACL L2 v4 v6 ACL Action v4 Action Macro v6 Action Macro

35

ACL Table Action

L2 Control Flow Graph Switch Pipeline

Resource constraints

v4 v6 ACL

Queues

Parser L2 Table IPv6 IPv4

L3 L2

v6 v4 L2 Action Macro v4 Action Macro v6 Action Macro Action ACL Table

36

Step 1: P4 Program Step 2: Control Flow Graph

L2 v4 v6 ACL 37

Step 3: Table Dependency Graph L2 v4 v6 ACL Step 4: Table Configuration

RMT Switch

1 2 3 4 32 …

RMT 32 Stages

Example

A Typical TDG

39

IPv6- Mcast EG- ACL1 EG- Phy- Meta IG-Agg- Intf IG- Dmac IPv4- Mcast IPv4- Nextho p IPv6- Nextho p IG- Props IG- Router- Mac Ipv4- Ecmp IG- Smac Ipv4- Ucast- LPM Ipv4- Ucast- Host Ipv6- Ucast- Host Ipv6- Ucast- LPM Ipv6- Ecmp IG_ACL 2 IG_Bca st_Stor m Ipv4_Ur pf Ipv6_Ur pf IG_ACL 1 EG_Pro ps IG_Phy _Meta

Configuration for RMT

Area Comparison with Fixed Function Switches

Section Area % of chip Extra Cost I/O, buffer, queue, CPU, etc 37% 0.0% Match memory & logic 54.3% 8.0% VLIW action engine 7.4% 5.5% Parser + deparser 1.3% 0.7% Total extra area cost 14.2%

Design goals of P4

• Reconfigurability

– Redefine packet parsing and processing

• Protocol independence

– Cannot be tied to specific packet formats

• Target independence

– Does not need to know the underlying switch hardware

The abstract forwarding model

P4 Concepts

• Headers
• Parsers
• Tables
• Actions

An example P4 program

The packet parser

Table specification

Action specifications

The control program

• Implements a control diagram

The control program

P4 primitive actions

• set field: Set a specific field in a header to a value.
• copy field: Copy one field to another.
• add header: Set a specific header instance (and all its
• fields) as valid.
• remove header: Delete (“pop”) a header (and all its fields)
• from a packet.
• increment: Increment or decrement the value in a field.
• checksum: Calculate a checksum over some set of header
• fields (e.g., an IPv4 checksum).

P4 compiler

• Compiles the program into target-specific

configurations

• Packet parser à state machine
• Control program à target dependency graphs

Discussion

• Is P4 the right language?
• Is match-action the right abstraction?

New idea: Packet Transactions

Summary

• Completes our coverage of modern networking

– SDN – NFV – Programmable switches

• P4
• Match-Action Tables