Commercial CAD: Challenges and Opportunities Ted Vucurevich CTO - - PowerPoint PPT Presentation

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Commercial CAD:

Challenges and Opportunities

Ted Vucurevich CTO – Advanced Research and Development Cadence Design Systems

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Agenda

• Commercial CAD: Today’s Problems
• Tomorrow’s Opportunities
• Conclusions

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Quiz #1

Commercial CAD is?

• 1. Too Expensive
• 2. Too Late to solve my “real” problems
• 3. Too Complicated
• 4. Too Important to ignore

Answer: It Depends on your viewpoint

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Many Late-Era CMOS Silicon Challenges

Very low supply voltages Feature size & spacing approach lithography limits Very high-performance chips (1GHz+) Very large chips (100MG+) Defect yields, process variation impacts, design rule complexity Scalability of EDA infrastructure, low-power design techniques, analog and digital together, handling analog IP Guardbands and process variation consume much of clock cycle, some new design techniques needed Increasing leakage power, pervasive signal integrity issues Pipelined HW / SW Co-Design mandatory Design cost 4X vs. 130nm Mask costs 2X vs. 90nm

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What is Manufacturable?

Design Rule Complexity

1 2 3 4 250 nm 180 nm 130 nm 90 nm 65 nm Node Normalized Pages

Increasing lithographic complexity is driving increasingly complex design rules. Source: Mark Mason (TI)

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Modeling at 65nm and beyond

Source: David Overhauser

Sidewall capacitance dominates Complex 3D structures

Net to Extract

3d Pattern Based Modeling

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Physical Data Organization must evolve

What’s in the Box? Who’s my neighbor?

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Variability is a First Class design concern

Hot Spot

Runtime SW Dependent

1 Atom = 25% Isub

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Drivers Component Plug-in

Component Software Integration mechanism Control and coordination of the Engines

Next Gen Architecture will be needed

Modelers Analyzers Synthesizers Verifiers

Transaction layer Open Access

Unified Persistent Data Model Thread Safe Run-time Data transactions

Re-entrant Heterogeneous Incremental Hierarchical Peer - Peer

Applications

Components Data Control

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Multi-Objective Optimization Necessary

Timing Area Timing Area Dynamic Power Leakage Power DFT Inc 26%

Remap 8%

Global map 66%

Inc

25%

Global map 75%

Old Approach Global Approach

Area

15%

Timing

85%

DFT

Leakage Power

Dynamic Power

Typical 2x to 5x faster Parallel

Global Multi- Dimension Runtime

Slack Die Size Leakage Power

Old synthesis = -2.893ns 9.07mm2 13.9 mW RC w/ scan, power = -0.384ns 8.10mm2 6.01 mW

Consumer Device

• 500k gates + 10 RAMs
• 130nm process
• 5 clocks

– Fastest=200MHz

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The CAD Eco-System is changing

Customer Integration

Today

Customer Integration

Tomorrow

Differentiation

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Answers to the most pressing questions about Commercial CAD today:

• 1. 3.5
• 2. The ones you would expect
• 3. Yes
• 4. No
• 5. Yes. Micro and Nano Systems
• 6. 42

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Agenda

• Commercial CAD: Today’s Problems
• Tomorrow’s Opportunities
• Conclusions

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It’s the System Stupid

Macro-Systems Meters 1891 Micro-Systems Centimeters 1947 Nano-Systems Millimeters 1993

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Electronic System and Architectural Design

Source: Jan Rabaey UCB

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Micro-Chips to Micro-Systems

System-in-Package (SiP) 3D Systems

2nd IC Level 1st IC Level TSV (drawn) Direct Bond

Ziptronix

Logic/ Cores Mem ory DRAM Flash Mem ory Bio-Sensor

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MicroFluidics: Answers for Power?

Microfluidic Channels

The researchers concluded it should be possible to remove a heat flux of 100 W/cm2 with a pressure drop of <2 atmospheres.

(Source: Georgia Institute of Technology)

“Firebolt ™” Chip level Thermal Analysis

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Photonics: Next-Gen Micro-Optical Systems

SOI MOS WaveGuide

Luxtera 10Gbit CMOS Photonics Platform

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Lab-on-a-chip: Next-Gen Micro-Bio Systems

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Next-Gen Molecular Analysis

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Nano-Systems: The Next Frontier

Carbon Nano-tube Manufacturing

Artificial Blood: Robert A. Freitas Jr.

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Evolving CMOS: One material at a time

Gate Silicon Substrate 1.2nm SiO2

65nm Gate Oxide

~1nm Molecular Storage Element ZettaRam Memory Cell 1mb Molecular DRAM

Molecular Material

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Nano Computing

Wires:

NanoTubes

=

Gates:

NanoFabrics

GigaGate Capacity!

After: Butts, DeHon, and Goldstein (ICCAD 2002)

Devices:

Memory, Gates

+

ZettaCore Memory

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Moore’s Law: You haven’t seen anything yet!

1.E-06 1.E-03 1.E+00 1.E+03 1.E+06 1.E+09 1880 1900 1920 1940 1960 1980 2000

doubles every 7.5 years

Ops/sec/$

Mechanical / Relays

doubles every 2.3 years

Tubes/ Transistor

2010 2020 203 1.E+10 1.E+11

doubles every 1.5 years

CMOS nanometer

doubles every few months?

Seth Copen Goldstein (CMU)

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Agenda

• Commercial CAD: Today’s Problems
• Tomorrow’s Opportunities
• Conclusions

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Conclusions: More Answers than Questions

• No
• Tremendous Opportunities in Micro and Nano

Systems

• Modeling, Analysis, Optimization
• EE’s, CS’s, Bio, Chemical, Medical, Mechanical,

Optical, Physics, Mathematics

• Yes

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Conclusion: The Whole Story

• Is Commercial EDA Dead?

– No

• Why not?

– Tremendous Opportunities in Micro and Nano Systems

• In what fundamental areas?

– Modeling, Analysis, Optimization

• What will the micro and nano-system design teams look

like?

– EE’s, CS’s, Bio, Chemical, Medical, Mechanical, Optical, Physics, Mathematics

• Are you glad you are still in CAD?

– Yes!!!