Building a basic membrane computer Alejandro Millan, Julian Viejo, - PowerPoint PPT Presentation

Building a basic membrane computer Alejandro Millan, Julian Viejo, Juan Quiros, et al. 14th Brainstorming Week on Membrane Computing, Feb. 1-5, 2016 Grupo ID2 (Investigacion y Desarrollo Digital) www.dte.us.es/id2 Dept. Tecnologia Electronica - Universidad de Sevilla (Spain)

Introduction Until now, developments have been focused into improving simulation time of P systems: ● Software simulation.- ○ RGNC (USe), Ciobanu, UniVr, … ● Hardware simulation.- ○ UPM, Petreska, Nguyen, Quiros, …

Objective ● Build a basic membrane computer.- Requisites ● Real machine: not simulated (1 transition/cycle).- ● Non-deterministic.- ● Maximum parallelism ( maxpar derivation mode).-

The chosen P systems [Pãun, 2000] Computer 1 Computer 2 n 2 generator ( n >= 1 ).- Divisor test ( k divides n ?).-

FPGA Technology (I) ● FPGA = Field- Programmable Gate Array.- ● Resources: ○ Look-Up-Tables (logic).- ○ Flip-Flops (memory).- ○ Arithmetic: ■ Distributed.- ■ Especific (MULT).- Training board

FPGA Technology (II) ● Design: ○ Hardware Description Language (HDL).- ○ Place & Routing.- ○ Reconfigurable.- ● Applications: ○ Prototyping.- ○ Quick deployment.- ○ Low production.- Training board

Object/rule implementation r 1 : f ff + � f REG f Logic r 1 � f

Competition - Case 1 (Algorithm) 1. Randomly let: r 1 : a ab’ a = a 1 + a 2 r 2 : a b’ � 2. Apply r 1 x a 1 times and r 2 x a 2 times.-

Competition - Case 1 (Design) r 1 : a ab’ r 2 : a b’ � LFSR + � a REG a Distribution a 1 � b’ 1 Logic r 1 � b’ 1 + REG b’ a 2 � b’ 2 � a Logic r 2 � b’ 2 + �� REG � ��

Competition - Case 2 (Algorithm) 1. Randomly let: a = a 1 + a 2 2. Let: r 1 : ac c’ � 1 = max{ 0 ; a 1 - c } r 2 : ac’ c � 2 = max{ 0 ; a 2 - c’ } � 1 = min{ c ; a 1 + � 2 } � 2 = min{ c’ ; a 2 + � 1 } 3. Apply r 1 x � 1 times and r 2 x � 2 times.-

Competition - Case 2 (Design) r 1 : ac c’ r 2 : ac’ c � a 1 + REG a � a 1 LFSR � a 2 Distribution a 1 + � 2 � c 1 � c 1 Logic r 1 + REG c � c’ 1 � c 2 a 2 + � 1 � c’ 1 � a 2 Logic r 2 + REG c’ � c’ 2 � c 2 � c’ 2

System interface - Computer 2 n Number Answer k Number Seed Clock Master reset Reset Data Valid

Operation detail - Computer 2 r1 r2 r1 r3 a a a c c c’ c’ d � c c’ d r1 r3 r2 r4

Schematic - Computer 2 (LFSR) MUX r21 a 2 MUX XOR LFSR D

Schematic - Computer 2 (object a ) ADDER r21 REG a 2 LFSR

Schematic - Computer 2 (rule r21 ) MULT r21 a 2 COMPARATORS LFSR REG

Implementation information FPGA Model Spartan 3E-1200 Clock frequency 50 MHz Performance 50 Mtransition/s Register width 16-bit FPGA Occupation 2% / 5% slices

Future work ● Test architectures in more powerful FPGAs.- ○ 50 MHz >>> 500 MHz.- ○ 20 K logic c. >>> 2 M logic c.- ● Build membrane computers for another P systems.- ○ More object competition.- ○ Consider rule probability (e.g. for PDP).- ○ Any suggestions?