Decoders and Trees 2 n 1 2 n 1 AND (2 n 1 ) AND (2 n 1 ) y [2 n - - PowerPoint PPT Presentation

SLIDE 1

Decoders and Trees

• n > 1 (recursion step)

AND(2n−1) AND(2n−1) 2n−1 2n−1 2n−1 Decoder’(n-1) y[2n − 1 : 2n−1] y[2n−1 − 1 : 0] n − 1 x[n − 2 : 0] x[n − 1] x[0] y[0] y[1] n = 1 (base)

Decoder’(n)

R[2k − 1 : 0] Decoder(n − k) Decoder(k) xL[n − k − 1 : 0] x[n − 1 : k]

• xR[k − 1 : 0] x[k − 1 : 0]

k 2k

2n−k × 2k array of AND-gates Q[2n−k − 1 : 0]

n − k 2n−k

R[r] ANDq,r y[q · 2k + r] Q[q]

Decoder(n) design shown and proven in class:

21 2n−1

xR[n − 2 : 0] x[n − 2 : 0] Decoder(n − 1) Decoder(1) Q[21 − 1 : 0] = Q[1 : 0]

1 n − 1

21 × 2n−1 array of AND-gates xL[0 : 0] x[n − 1 : n − 1]

• R[2n−1 − 1 : 0]

x[n − 1] AND(2n−1) AND(2n−1) 2n−1 2n−1 2n−1 Decoder’(n-1) y[2n − 1 : 2n−1] y[2n−1 − 1 : 0] n − 1 x[n − 2 : 0]

for k = n-1:

y[1] x[0] y[0]

Decoder(1)

Decoder’(n)

SLIDE 2

Decoder’(n) is a private case of Decoder(n) design. (k = n-1 or k = 1) Decoder’(n) is a correct implementation of a decoder.

• therwise

2 2 ) 1 ( 1 n if

1

INV c AND c n c INV c n c

n

Cost analysis: Solving the recurrence:

• INV

c AND c n c n c

n

• 2

1

• INV

c n AND c c

n n

• 1

2 2 2 1

2 1

• AND

c INV c n

n

• 1

2 1 2 2

1 2

• AND

c INV c n

n

• 4

2

1 n

2

• :

1

• n

asymptotics

• therwise

1 , max 1 n if ) ( AND d n d INV d INV d n d

• AND

d n d INV d n d

• 1

, max

• AND

d n d

• 1
• AND

d n d 1 1

• AND

d n INV d 1

• n
• Linear Delay!!!

Delay analysis: Solving the recurrence:

: 1

• n
• therwise

: 1 : 1 1 2 , mod

2 2

2

n n

x I i A

n

• therwise

: 1 : 1 1 2

2 2

2

n n

n x n I i B

n

Decoder(n) for k = n/2

Decoder(n/2) Decoder(n/2) x[n/2 − 1 : 0] x[n − 1 : n/2] B[2n/2 − 1 : 0] A[2n/2 − 1 : 0] AND (i ∈ {0, 1, . . ., 2n − 1}) B[⌊i/2n/2⌋] A[i mod 2n/2] Y [i]

Consider the top two recursion steps: each AND-gate in the “AND-gates array” of the second recursion step, i.e. Decoder(n/2), feeds 2n/2 AND-gates in the “AND-gates array” of the primary recursion step, i.e. Decoder(n).

2

2 net a

• f

fanout Maximum

n

• therwise

2 2 1 n if

2

AND c c INV c n c

n n n

2

• therwise

1 n if ) (

2

AND d d INV d n d

n

• n

log

SLIDE 3

31 9 16 15 7 8

• 4
• 2

1 1 1 Decoder’(n) Decoder(n) k=n/2 Design n 262152 132304 16 1024 616 8 60 52 4 10 10 2 1 1 1 Decoder’(n) Decoder(n) k=n/2 Design n

Cost Delay

Balanced Trees

OR OR-Tree(n/2) OR-Tree(n/2)

2 n 2 n

• therwise

1 n if

2

OR d d n d

n

• OR

d n n d

• 2

log

Logarithmic Delay Lower Bound Theorem: Let C = < G , N > denote a combinational circuit that implements a non-constant Boolean function f: {0,1}n {0,1}. If the fan-in of every gate in G is at most c, then the delay of C is at least logc|cone(f)|. cone(ORn) = n fan-in 2 delay(ORn) log2(n)·d(OR) Delay of the balanced tree is minimized.

Recursive algorithm for computing an OR-tree(n)

• 1. The case that n 2 is trivial.
• 2. If n > 2, then let a, b be any pair of positive integers such that

(i) n = a + b and (ii) max{log2a , log2b} log2n - 1.

• 3. Compute an OR-tree(a) and an OR-tree(b).

Connect their outputs to an OR-gate to obtain an OR-tree(n).

Claim: the above algorithm computes a minimum delay OR-tree.

We first show that for every n > 2 there exist a pair of positive numbers a, b such that:

n b a

• (i)
• 1

log log , log max (ii)

2 2 2

• n

b a

k

n 2 if

• 1

log log , log max

• bviously,

2 2 2

• n

b a 1

• k

1

• k

1 k

2 2 if

• k

n

k

a 2

• k

a

2

log

k k

n b 2 2

• k

b

2

log

• 1

log2

• k

n

1

2 2 : pair such

• ne

exists there

• k

n b a : set

• Note that this is the most

unbalanced partition of n, and still we get the minimal delay.

Proof:

SLIDE 4

Induction hypothesis: Induction step: we prove the claim for n,

• OR

d b tree OR d a tree OR d n tree OR d

• ,

max

• OR

d OR d b a

• 2

2

log , log max

• OR

d OR d n

• 1

log2

• OR

d k k tree OR d n k

• 2

log .

• OR

d n

• 2

log

• hypothesis

induction

We prove by induction on n that the delay of the computed OR-tree is log2n ·d(OR) to obtain delay minimality. Induction basis: n = 1 or n = 2 are trivial cases.

• 1

1

• buffer

c

• 1

1

• buffer

d 2

• fanout

A balanced tree structure minimizes the delay and cost. The tree is a binary tree due to fan-out limitations.

buffer

• 1

!

• buffer

d n n d

• 1

1 log2

• buffer

c n n c

• 1

2

Notice: * The leaves of the tree feed the gate outputs. * The root of the tree is fed by the gate input. * The first branching is free no need for a “root” gate.

Buffers

• buf

c tree buf c INV c AND c n c n c

n n

• 1

2 1 2 2 1

1

• buf

c INV c AND c n c

n n

• 1

3 2 2 1

Cost analysis:

x[n − 1] AND(2n−1) AND(2n−1) 2n−1 2n−1 2n−1 Decoder’(n-1) y[2n − 1 : 2n−1] y[2n−1 − 1 : 0] n − 1 x[n − 2 : 0]

1-buf-trees

• INV

c c

• 1

: 1

• n

: 1

• n

Fanout limitation effect on design

2

• fanout
• AND

d n d tree buf d buf d tree buf d INV d n d

n n

• "

# " $ % "

• "
• 1

2 1 1 2 1 max

1 1

Delay analysis:

• INV

d d

• 1

x[n − 1] AND(2n−1) AND(2n−1) 2n−1 2n−1 2n−1 Decoder’(n-1) y[2n − 1 : 2n−1] y[2n−1 − 1 : 0] n − 1 x[n − 2 : 0]

1-buf-trees

• AND

d n d buf d n buf d n INV d

• "

# " $ % "

• "
• 1

1 1 1 max : 1

• n

: 1

• n

SLIDE 5

• AND

d tree buf d d n d

n

n

• 2

2 1

2

• 2

2

2 1 2 2 2 2

2

n n

tree buf c AND c c n c

n n

• Cost analysis:

Delay analysis:

• buf

c AND c c

n n

n n

• 1

2 2 2 2 2

2 2 1

2

• INV

c c

• 1
• INV

d d

• 1
• AND

d buf d d

n n

• 1

1

2 2

: 1

• n

: 1

• n

: 1

• n

: 1

• n

Decoder(n/2) Decoder(n/2) x[n/2 − 1 : 0] x[n − 1 : n/2] B[2n/2 − 1 : 0] A[2n/2 − 1 : 0] AND (i ∈ {0, 1, . . ., 2n − 1}) B[⌊i/2n/2⌋] A[i mod 2n/2] Y [i]

1-buf-trees

Cost Decoder(n): n=1: 1 n=2: 10 n=4: 52 n=8: 616 n=16: 132304 n=32: 8.5902e+009 n=64: 3.68935e+019 n=128: 6.80565e+038 Cost Decoder‘(n): n=1: 1 n=2: 10 n=4: 60 n=8: 1024 n=16: 262152 n=32: 1.71799e+010 n=64: 7.3787e+019 n=128: 1.36113e+039 Cost Decoder‘(n), Fanout<=2: n=1: 1 n=2: 11 n=4: 79 n=8: 1511 n=16: 393175 n=32: 2.57698e+010 n=64: 1.1068e+020 n=128: 2.04169e+039 Cost Decoder(n), Fanout<=2: n=1: 1 n=2: 10 n=4: 68 n=8: 1096 n=16: 263312 n=32: 1.71801e+010 n=64: 7.3787e+019 n=128: 1.36113e+039 Delay Decoder(n): n=1: 1 n=2: 3 n=4: 5 n=8: 7 n=16: 9 n=32: 11 n=64: 13 n=128: 15 Delay Decoder‘(n): n=1: 1 n=2: 3 n=4: 7 n=8: 15 n=16: 31 n=32: 63 n=64: 127 n=128: 255 Delay Decoder‘(n), Fanout<=2: n=1: 1 n=2: 4 n=4: 8 n=8: 16 n=16: 32 n=32: 64 n=64: 128 n=128: 256 Delay Decoder(n), Fanout<=2: n=1: 1 n=2: 3 n=4: 6 n=8: 11 n=16: 20 n=32: 37 n=64: 70 n=128: 135