[PPT] - Bitline PUF: Daniel E. Holcomb Kevin Fu Building Native PowerPoint Presentation

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Sept 26, 2014 Cryptographic Hardware and Embedded Systems

Bitline PUF:

Building Native Challenge-Response PUF Capability into Any SRAM

Daniel E. Holcomb Kevin Fu University of Michigan

Acknowledgment: This work was supported in part by C-FAR, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by NSF CNS-1331652. Any opinions, findings, conclusions, and recommendations expressed in these materials are those of the authors and do not necessarily reflect the views of the sponsors.

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Holcomb and Fu Bitline PUF — CHES 2014

Context

2

CMOS PUFs

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Holcomb and Fu Bitline PUF — CHES 2014

Context

2

High-cost PUFs using custom circuitry CMOS PUFs

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Holcomb and Fu Bitline PUF — CHES 2014

Context

2

High-cost PUFs using custom circuitry CMOS PUFs Low-cost PUFs using existing circuitry

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Holcomb and Fu Bitline PUF — CHES 2014

Context

2

High-cost PUFs using custom circuitry CMOS PUFs Low-cost PUFs using existing circuitry This talk

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Holcomb and Fu Bitline PUF — CHES 2014

Contributions

3

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

SLIDE 7

Holcomb and Fu Bitline PUF — CHES 2014

Contributions

❖ Adding a few gates to wordline drivers of SRAM creates a new

PUF

3

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

SLIDE 8

Holcomb and Fu Bitline PUF — CHES 2014

Clk Eval Reset Enable

Contributions

❖ Adding a few gates to wordline drivers of SRAM creates a new

PUF

3

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

SLIDE 9

Holcomb and Fu Bitline PUF — CHES 2014

Clk Eval Reset Enable

Contributions

❖ Adding a few gates to wordline drivers of SRAM creates a new

PUF

❖ Bitline PUF ❖ Challenge-response operation ❖ Low area overhead ❖ Simple 3

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

SLIDE 10

Holcomb and Fu Bitline PUF — CHES 2014

Outline

1. Introduction

❖ PUFs ❖ SRAM ❖ Bitline PUF

2. Evaluation

❖ Uniqueness ❖ Reliability ❖ Modeling Attacks

3. Summary and Related work

4

SLIDE 11

Holcomb and Fu Bitline PUF — CHES 2014

Physical Unclonable Functions (PUFs)

❖ Map challenges to responses according to uncontrollable

physical variations

❖ Unique to each chip and persistent ❖ Random dopant fluctuations and small devices ❖ Balanced parasitics and wire lengths to avoid bias ❖ Applications include anti-counterfeiting and hardware metering

5

f

PUF Characterized by Challenge-Response Pairs (CRPs) Challenges Responses

SLIDE 12

Holcomb and Fu Bitline PUF — CHES 2014

6-Transistor SRAM Cell

❖ Ubiquitous memory ❖ Two stable states: “0” (AB=01) “1” (AB=10) ❖ Wordline selects a cell for reading/writing ❖ Complementary bitlines read/write values to/from selected cells

6

A B A B BL BLB wordline wordline BL BLB bitlines bitlines

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Holcomb and Fu Bitline PUF — CHES 2014

Reading an SRAM Cell

7

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1 Wordline Drivers Sense Amps Precharge Circuits

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Holcomb and Fu Bitline PUF — CHES 2014

Reading an SRAM Cell

7

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

BLi PRE

…

RE RE RE BLBi WL1

Wordline Drivers Sense Amps Precharge Circuits

SLIDE 15

Holcomb and Fu Bitline PUF — CHES 2014

Reading an SRAM Cell

7

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

BLi PRE

…

RE RE RE BLBi WL1

1

Wordline Drivers Sense Amps Precharge Circuits

SLIDE 16

Holcomb and Fu Bitline PUF — CHES 2014

Reading an SRAM Cell

7

PRE

(Precharge)

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

BLi PRE

…

RE RE RE BLBi WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns]

1

Wordline Drivers Sense Amps Precharge Circuits

SLIDE 17

Holcomb and Fu Bitline PUF — CHES 2014

Reading an SRAM Cell

7

PRE

(Precharge)

WL1

(Wordline)

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

BLi PRE

…

RE RE RE BLBi WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

1

Wordline Drivers Sense Amps Precharge Circuits

SLIDE 18

Holcomb and Fu Bitline PUF — CHES 2014

Reading an SRAM Cell

7

PRE

(Precharge)

WL1

(Wordline)

RE

(Read Enable)

… …

Word 0 Word 1 Word Y-1

1 1 1 1 1 1

BLi PRE

…

RE RE RE BLBi WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

1

Wordline Drivers Sense Amps Precharge Circuits

SLIDE 19

Holcomb and Fu Bitline PUF — CHES 2014

Bitline PUF

❖ Accumulate wordline enable signals for concurrent read ❖ Concurrent reading causes contention ❖ Contention resolves according to variations

8

… …

Word 0 Word 1 Word Y-1

1 1 1 1

Clk Eval Reset Enable

✓ ✓

SLIDE 20

Holcomb and Fu Bitline PUF — CHES 2014

Bitline PUF

❖ Accumulate wordline enable signals for concurrent read ❖ Concurrent reading causes contention ❖ Contention resolves according to variations

8

… …

Word 0 Word 1 Word Y-1

1 1 1 1

Write SRAM cells Load WL Drivers

Read Clk Eval Reset Enable

✓ ✓

SLIDE 21

Holcomb and Fu Bitline PUF — CHES 2014

Bitline PUF

❖ Accumulate wordline enable signals for concurrent read ❖ Concurrent reading causes contention ❖ Contention resolves according to variations

8

… …

Word 0 Word 1 Word Y-1

1 1 1 1

Write SRAM cells Load WL Drivers

Read Clk Eval Reset Enable

✓ ✓

SLIDE 22

Holcomb and Fu Bitline PUF — CHES 2014

Write SRAM cells Load WL Drivers

Read

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1

1 1

WL0

✓ ✓

SLIDE 23

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1

1 1

WL0

✓ ✓

SLIDE 24

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

1 1

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 25

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

1 1

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 26

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

1 1

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 27

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1 WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 28

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns]

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 29

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns]

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 30

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

❖ Largely consistent over time for

given column

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns]

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 31

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

❖ Largely consistent over time for

given column

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 32

Holcomb and Fu Bitline PUF — CHES 2014

Reading a Bitline PUF

❖ Read with contention ❖ Contention resolves according

to variation

❖ Largely consistent over time for

given column

❖ Varies across columns or chips

9

BLi PRE

…

RE RE RE BLBi WL1 WL0 WL1

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

WL0

0.4 0.8 1.2 1 2 3 Voltage Time [ns] 0.4 0.8 1.2 1 2 3 Voltage Time [ns]

✓ ✓

SLIDE 33

Holcomb and Fu Bitline PUF — CHES 2014

Challenge Response Pairs

❖ PUF Challenge: ❖ 4 possible challenges (Y = num. rows) ❖ For each cell in column:

1. wordline on, cell value 0
2. wordline on, cell value 1
3. wordline off, cell value 0
4. wordline off, cell value 1

❖ PUF Response: ❖ Value read by sense amp of column(s)

10

Y

1 ✓ ✓ 1

SLIDE 34

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

SLIDE 35

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

1 1

SLIDE 36

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

1 1 1

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Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

1 1 1

✓

SLIDE 38

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

1 1 1

✓ ✓

SLIDE 39

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

X X X X X X 1

✓ ✓

SLIDE 40

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

X X X X X X 1

SLIDE 41

Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

❖ Word-parallel (e.g. 256 columns) ❖ Response latency ❖ 6 cycles for 256-bit response as shown ❖ Depends on number of enabled rows

X X X X X X 1

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Holcomb and Fu Bitline PUF — CHES 2014

Performance and Overhead

11

… …

Word 0 Word 1 Word Y-1

1 1

Write SRAM cells

≤ Y Cycles

Load Challenge

Load WL Drivers

≤ Y Cycles

Read

1 Cycle

Eval. Responses

❖ Word-parallel (e.g. 256 columns) ❖ Response latency ❖ 6 cycles for 256-bit response as shown ❖ Depends on number of enabled rows ❖ Area overhead ❖ A few extra gates per SRAM row ❖ Don’t need to add circuitry on all rows

X X X X X X 1

SLIDE 43

Holcomb and Fu Bitline PUF — CHES 2014

Integration

❖ Simple digital interface ❖ No power-cycling required ❖ Non-exclusive, SRAM rows still usable as memory when not used for PUF ❖ Does not upset stored data in non-used rows

12

… …

Word 0 Word 1 Word Y-1

Clk Eval Reset Enable

SLIDE 44

Holcomb and Fu Bitline PUF — CHES 2014

Outline

1. Introduction

❖ PUFs ❖ SRAM ❖ Bitline PUF

2. Evaluation

❖ Uniqueness ❖ Reliability ❖ Modeling Attacks

3. Summary and Related work

13

SLIDE 45

Holcomb and Fu Bitline PUF — CHES 2014

Methodology

❖ Circuit simulation using Ngspice ❖ Devices are 90nm Predictive Technology Model [1] ❖ Sizing according to Nii et al. [2] ❖ Variation: threshold voltage and channel length [3,4] ❖ Noise: between cross-coupled nodes [5]

14

+

—

+

—

experiment code available online: https://github.com/danholcomb/bitline-puf

n4 n3 n2 n1 p1 p2

µ

σ µ σ

[1] Predictive Technology Model. 90nm NMOS and PMOS BSIM4 Models

[2] Nii et al., IEEE Journal of Solid State Circuits, 2004 [3] Pelgrom et al. IEEE Journal of Solid State Circuits, 1989 [4] Seevinck et al. IEEE Journal of Solid State Circuits, 1987 [5] Anis et al. Workshop on System-on-Chip for Real-Time Applications, 2005

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Holcomb and Fu Bitline PUF — CHES 2014

Choosing Useful Challenges

15

… …

Word 0 Word 1 Word Y-1

1 1 1

✓ ✓

… …

Word 0 Word 1 Word Y-1

1 1 1 1

✓ ✓

SLIDE 47

Holcomb and Fu Bitline PUF — CHES 2014

Choosing Useful Challenges

15

… …

Word 0 Word 1 Word Y-1

1 1 1

✓ ✓

… …

Word 0 Word 1 Word Y-1

1 1 1 1

✓ ✓

SLIDE 48

Holcomb and Fu Bitline PUF — CHES 2014

Choosing Useful Challenges

❖ Useful challenges have equal number of 0s and 1s ❖ Exponential subset of the 4Y possible challenges

16

(Asymmetric designs may have different useful challenges)

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Num. 1s in Challenge
Num. 0s in Challenge

0% 10% 20% 30% 40% 50%

Prob. of Diff. Response

1e+02 1e+06 1e+10 1e+14 16 20 24 28 32

Num. of Challenges

Y (Num. of SRAM Rows) equal 0/1 2Y

SLIDE 49

Holcomb and Fu Bitline PUF — CHES 2014

Uniqueness and Reliability

❖ Applying random challenges with equal number 0s and 1s ❖ Nominal conditions: 1.2V and 27°C

17

0.25 0.50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency Hamming Distance Between 32-bit Responses Within-Class Between-Class

SLIDE 50

Holcomb and Fu Bitline PUF — CHES 2014

Uniqueness and Reliability

❖ Applying random challenges with equal number 0s and 1s ❖ Nominal conditions: 1.2V and 27°C

17

0.25 0.50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency Hamming Distance Between 32-bit Responses Within-Class Between-Class

Nominal BER is 2.3%

SLIDE 51

Holcomb and Fu Bitline PUF — CHES 2014

Uniqueness and Reliability

❖ Applying random challenges with equal number 0s and 1s ❖ Nominal conditions: 1.2V and 27°C

17

0.02 0.04 0.06 0.08 20 40 60 80 BER vs 27°C Temperature [C] 0.02 0.04 0.06 0.08 1.1 1.15 1.2 1.25 1.3 BER vs 1.2 V Supply Voltage [V] 0.25 0.50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency Hamming Distance Between 32-bit Responses Within-Class Between-Class

Nominal BER is 2.3%

SLIDE 52

Holcomb and Fu Bitline PUF — CHES 2014

Uniqueness and Reliability

❖ Applying random challenges with equal number 0s and 1s ❖ Nominal conditions: 1.2V and 27°C

17

0.02 0.04 0.06 0.08 20 40 60 80 BER vs 27°C Temperature [C] 0.02 0.04 0.06 0.08 1.1 1.15 1.2 1.25 1.3 BER vs 1.2 V Supply Voltage [V] 0.25 0.50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency Hamming Distance Between 32-bit Responses Within-Class Between-Class

Nominal BER is 2.3%

BER ≤ 7.6% across voltage and temperature

SLIDE 53

Holcomb and Fu Bitline PUF — CHES 2014

Modeling Attacks

❖ Can a model predict Bitline PUF’s responses? (Yes)

18

❖ Challenge values

1. WL on, value 0
2. WL on, value 1
3. WL off, value 0
4. WL off, value 1

1

✓ ✓

1 1 3 2

[1] Joachims. Making large-Scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 1999

SLIDE 54

Holcomb and Fu Bitline PUF — CHES 2014

Modeling Attacks

❖ Can a model predict Bitline PUF’s responses? (Yes)

18

❖ Challenge values

1. WL on, value 0
2. WL on, value 1
3. WL off, value 0
4. WL off, value 1

1

✓ ✓

1 1 3 2

1 0 0 0 0 0 1 0 0 1 0 0 1

[1] Joachims. Making large-Scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 1999

SLIDE 55

Holcomb and Fu Bitline PUF — CHES 2014

Modeling Attacks

❖ Can a model predict Bitline PUF’s responses? (Yes)

18

❖ Challenge values

1. WL on, value 0
2. WL on, value 1
3. WL off, value 0
4. WL off, value 1

1

✓ ✓

1 1 3 2

Classification using SVM

light [1]

1 0 0 0 0 0 1 0 0 1 0 0 1

50% 60% 70% 80% 90% 100% 100 200 300 400 500 Prediction Accuracy Size of Training Set PUF A PUF B PUF C

[1] Joachims. Making large-Scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 1999

SLIDE 56

Holcomb and Fu Bitline PUF — CHES 2014

Modeling Attacks

❖ Can a model predict Bitline PUF’s responses? (Yes)

18

❖ Challenge values

1. WL on, value 0
2. WL on, value 1
3. WL off, value 0
4. WL off, value 1

1

✓ ✓

1 1 3 2

Classification using SVM

light [1]

1 0 0 0 0 0 1 0 0 1 0 0 1

50% 60% 70% 80% 90% 100% 100 200 300 400 500 Prediction Accuracy Size of Training Set PUF A PUF B PUF C

❖ CRPs must be obfuscated as

usual (Mission Impossible?)

[1] Joachims. Making large-Scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 1999

SLIDE 57

Holcomb and Fu Bitline PUF — CHES 2014

Outline

1. Introduction

❖ PUFs ❖ SRAM ❖ Bitline PUF

2. Evaluation

❖ Uniqueness ❖ Reliability ❖ Modeling Attacks

3. Summary and Related work

19

SLIDE 58

Holcomb and Fu Bitline PUF — CHES 2014

Related Work

❖ SRAM PUFs [1,2,3] ❖ Bistable-ring PUF [4] ❖ Low-power current PUF [5]

20

[1] Guajardo et al. CHES 2007

[2] Holcomb et al. T-Comp 2009 [3] Zheng et al. DAC 2013 [4] Chen et al. HOST 2011 [5] Majzoobi et al. ISCAS 2011

SLIDE 59

Holcomb and Fu Bitline PUF — CHES 2014

Bitline PUF: Summary

21

❖ Modifying wordline drivers of SRAM array creates a new PUF with desirable

properties

❖ Challenge-response operation ❖ Low area overhead ❖ Simple

Write SRAM cells Load Challenge Load WL Drivers Read

Eval. Responses

Clk Eval Reset Enable

… …

1 1 1 1 1 1

SLIDE 60

Holcomb and Fu Bitline PUF — CHES 2014

Bitline PUF: Summary

21

❖ Modifying wordline drivers of SRAM array creates a new PUF with desirable

properties

❖ Challenge-response operation ❖ Low area overhead ❖ Simple

Write SRAM cells Load Challenge Load WL Drivers Read

Eval. Responses

Questions?

Clk Eval Reset Enable

… …

1 1 1 1 1 1

SLIDE 61

Holcomb and Fu Bitline PUF — CHES 2014

Backup: Power Consumption

22 1.2 0 0.5 1 1.5 2 2.5 3 100 200 300 400 500 Voltage Current [uA] Time [ns] 1.2 0 0.5 1 1.5 2 2.5 3 100 200 300 400 500 Voltage Current [uA] Time [ns] V(PRE) V(WL) V(RE) V(BL) V(BLB) I(VDD) 25 50 75 100 2 4 6 8 10 12 14 16 Average Power [uW] Number of Rows Active in Challenge SRAM Read Bitline PUF Eval