Sept 26, 2014 Cryptographic Hardware and Embedded Systems Bitline PUF: � Daniel E. Holcomb Kevin Fu Building Native Challenge-Response University of Michigan PUF Capability into Any SRAM Acknowledgment: This work was supported in part by C-FAR, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by NSF CNS-1331652. Any opinions, findings, conclusions, and recommendations expressed in these materials are those of the authors and do not necessarily reflect the views of the sponsors.
Context � CMOS PUFs 2 Holcomb and Fu Bitline PUF — CHES 2014
Context � CMOS PUFs High-cost PUFs using custom circuitry 2 Holcomb and Fu Bitline PUF — CHES 2014
Context � CMOS PUFs High-cost PUFs using Low-cost PUFs using custom circuitry existing circuitry 2 Holcomb and Fu Bitline PUF — CHES 2014
Context � CMOS PUFs High-cost PUFs using Low-cost PUFs using custom circuitry existing circuitry This talk 2 Holcomb and Fu Bitline PUF — CHES 2014
Contributions Word 0 1 0 1 1 1 Word 1 0 … … 1 0 Word Y-1 1 3 Holcomb and Fu Bitline PUF — CHES 2014
Contributions ❖ Adding a few gates to wordline drivers of SRAM creates a new PUF Word 0 1 0 1 1 1 Word 1 0 … … 1 0 Word Y-1 1 3 Holcomb and Fu Bitline PUF — CHES 2014
Contributions ❖ Adding a few gates to wordline drivers of SRAM creates a new PUF Word 0 1 0 1 1 1 Word 1 0 Enable … … Clk Reset Eval 1 0 Word Y-1 1 3 Holcomb and Fu Bitline PUF — CHES 2014
Contributions ❖ Adding a few gates to wordline drivers of SRAM creates a new PUF ❖ Bitline PUF ❖ Challenge-response operation ❖ Low area overhead ❖ Simple Word 0 1 0 1 1 1 Word 1 0 Enable … … Clk Reset Eval 1 0 Word Y-1 1 3 Holcomb and Fu Bitline PUF — CHES 2014
Outline 1. Introduction ❖ PUFs ❖ SRAM ❖ Bitline PUF 2. Evaluation ❖ Uniqueness ❖ Reliability ❖ Modeling Attacks 3. Summary and Related work 4 Holcomb and Fu Bitline PUF — CHES 2014
Physical Unclonable Functions (PUFs) ❖ Map challenges to responses according to uncontrollable physical variations ❖ Unique to each chip and persistent ❖ Random dopant fluctuations and small devices ❖ Balanced parasitics and wire lengths to avoid bias ❖ Applications include anti-counterfeiting and hardware metering Challenges Responses f PUF Characterized by Challenge-Response Pairs (CRPs) 5 Holcomb and Fu Bitline PUF — CHES 2014
6-Transistor SRAM Cell ❖ Ubiquitous memory ❖ Two stable states: “0” (AB=01) “1” (AB=10) ❖ Wordline selects a cell for reading/writing ❖ Complementary bitlines read/write values to/from selected cells wordline wordline B B A A bitlines bitlines BLB BL BLB BL 6 Holcomb and Fu Bitline PUF — CHES 2014
Reading an SRAM Cell Precharge Circuits Wordline Drivers 1 1 Word 0 0 1 1 Word 1 0 … … 0 1 Word Y-1 1 Sense Amps 7 Holcomb and Fu Bitline PUF — CHES 2014
Reading an SRAM Cell Precharge Circuits PRE Wordline Drivers 1 1 Word 0 0 1 1 Word 1 0 … … WL 1 0 1 Word Y-1 1 … BL i BLB i Sense Amps RE RE RE 7 Holcomb and Fu Bitline PUF — CHES 2014
Reading an SRAM Cell Precharge Circuits PRE Wordline Drivers 1 1 Word 0 0 1 1 Word 1 0 … … WL 1 0 1 0 1 Word Y-1 1 … BL i BLB i Sense Amps RE RE RE 7 Holcomb and Fu Bitline PUF — CHES 2014
Reading an SRAM Cell Precharge Circuits PRE Wordline Drivers 1 1 Word 0 0 1 1 Word 1 0 … … WL 1 0 1 0 1 Word Y-1 1 … BL i BLB i Sense Amps 1.2 0.8 Voltage RE RE 0.4 PRE � (Precharge) 0 0 1 2 3 RE Time [ns] 7 Holcomb and Fu Bitline PUF — CHES 2014
Reading an SRAM Cell Precharge Circuits PRE Wordline Drivers 1 1 Word 0 0 1 1 Word 1 0 … … WL 1 0 1 0 1 Word Y-1 1 … BL i BLB i Sense Amps 1.2 1.2 0.8 0.8 Voltage Voltage RE RE 0.4 0.4 PRE � WL 1 � (Precharge) (Wordline) 0 0 0 0 1 1 2 2 3 3 RE Time [ns] Time [ns] 7 Holcomb and Fu Bitline PUF — CHES 2014
Reading an SRAM Cell Precharge Circuits PRE Wordline Drivers 1 1 Word 0 0 1 1 Word 1 0 … … WL 1 0 1 0 1 Word Y-1 1 … BL i BLB i Sense Amps 1.2 1.2 1.2 0.8 0.8 0.8 Voltage Voltage Voltage RE RE 0.4 0.4 0.4 PRE � WL 1 � RE � (Precharge) (Wordline) (Read Enable) 0 0 0 0 0 0 1 1 1 2 2 2 3 3 3 RE Time [ns] Time [ns] Time [ns] 7 Holcomb and Fu Bitline PUF — CHES 2014
Bitline PUF ❖ Accumulate wordline enable signals for concurrent read ❖ Concurrent reading causes contention ❖ Contention resolves according to variations ✓ Word 0 1 0 1 ✓ Enable 1 1 Word 1 0 … … Clk Reset Eval Word Y-1 8 Holcomb and Fu Bitline PUF — CHES 2014
Bitline PUF ❖ Accumulate wordline enable signals for concurrent read ❖ Concurrent reading causes contention ❖ Contention resolves according to variations ✓ Word 0 1 0 1 ✓ Enable 1 1 Word 1 0 … … Clk Reset Eval Word Y-1 Write SRAM cells Load WL Drivers Read 8 Holcomb and Fu Bitline PUF — CHES 2014
Bitline PUF ❖ Accumulate wordline enable signals for concurrent read ❖ Concurrent reading causes contention ❖ Contention resolves according to variations ✓ Word 0 1 0 1 ✓ Enable 1 1 Word 1 0 … … Clk Reset Eval Word Y-1 Write SRAM cells Load WL Drivers Read 8 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation 0 1 ✓ WL 1 1 0 … BL i BLB i RE RE Write SRAM cells Load WL Drivers Read RE 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation 0 1 ✓ WL 1 1 0 … BL i BLB i RE RE RE 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation 0 1 ✓ WL 1 1 0 … BL i BLB i 1.2 0.8 Voltage RE RE 0.4 WL 0 � WL 1 0 0 1 2 3 RE Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation 0 1 ✓ WL 1 1 0 … BL i BLB i 1.2 0.8 Voltage RE RE 0.4 WL 0 � WL 1 0 0 1 2 3 RE Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation 0 1 ✓ WL 1 1 0 … BL i BLB i 1.2 1.2 0.8 0.8 Voltage Voltage RE RE 0.4 0.4 WL 0 � WL 1 0 0 0 0 1 1 2 2 3 3 RE Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation ✓ WL 1 … BL i BLB i 1.2 1.2 0.8 0.8 Voltage Voltage RE RE 0.4 0.4 WL 0 � WL 1 0 0 0 0 1 1 2 2 3 3 RE Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation ✓ WL 1 … BL i BLB i 1.2 1.2 1.2 0.8 0.8 0.8 Voltage Voltage Voltage RE RE 0.4 0.4 0.4 WL 0 � WL 1 0 0 0 0 0 0 1 1 1 2 2 2 3 3 3 RE Time [ns] Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation ✓ WL 1 … BL i BLB i 1.2 1.2 1.2 0.8 0.8 0.8 Voltage Voltage Voltage RE RE 0.4 0.4 0.4 WL 0 � WL 1 0 0 0 0 0 0 1 1 1 2 2 2 3 3 3 RE Time [ns] Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation ❖ Largely consistent over time for ✓ WL 1 given column … BL i BLB i 1.2 1.2 1.2 0.8 0.8 0.8 Voltage Voltage Voltage RE RE 0.4 0.4 0.4 WL 0 � WL 1 0 0 0 0 0 0 1 1 1 2 2 2 3 3 3 RE Time [ns] Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation ❖ Largely consistent over time for ✓ WL 1 given column … BL i BLB i 1.2 1.2 1.2 1.2 0.8 0.8 0.8 0.8 Voltage Voltage Voltage Voltage RE RE 0.4 0.4 0.4 0.4 WL 0 � WL 1 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 RE Time [ns] Time [ns] Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
Reading a Bitline PUF ❖ Read with contention PRE ❖ Contention resolves according ✓ WL 0 to variation ❖ Largely consistent over time for ✓ WL 1 given column ❖ Varies across columns or chips … BL i BLB i 1.2 1.2 1.2 1.2 0.8 0.8 0.8 0.8 Voltage Voltage Voltage Voltage RE RE 0.4 0.4 0.4 0.4 WL 0 � WL 1 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 RE Time [ns] Time [ns] Time [ns] Time [ns] 9 Holcomb and Fu Bitline PUF — CHES 2014
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