AICP – AURA Intelligent Co-Processor Jim Austin Advanced Computer Architectures Group, University of York Cybula Ltd.
AICP project • Concerted action with FAR (costs and people shared) • Started 1 August 2003 for 2 years. • AICP Collaborators – Cybula Ltd. – University of York
People • University of York – Prof. Jim Austin , Academic manager – Mike Weeks, Technical Lead – Mike Freeman, Technical and Amadeus link • Cybula – Dr. Sujeewa Alwis, Commercial manager
Motivation • Need low cost, embeddable pattern match engine • Many applications could benefit from this – face recognition, text matching, signal analysis • Cybula/UofY AURA technology has many applications already
Aims • To build an embeddable AURA core. – Use the existing PRESENCE II card as a platform. – Develop • AURA graph matcher – for face recognition • AURA CMM core – Support implanting the FAR application IP
Technology Cybula PRESENCE II Uses Vertex FPGA Large on board memory PCI based Basis of Cybulas FaceEnforce system
AURA core – The CMM Bit 1 2 Bit 7 3 4 Bit 2 5 6 7 8 Bit 4 Bit 1
The Compact Binary Vector Processor - CBV • AURA operations are based on manipulation of binary vectors. • Many applications. • The CBV implements the instruction set used to make CMMs etc. • Non-binary version also available
Outline architecture
Expected performance • 4 streams: – AMD Athlon XP2000+ with 256M RAM Verses – Virtex II FPGA, 133MHz with two streams = 1.27 ms. 3.5 - 6.9 speedup with four streams = 635 us. 7.1 - 13.8 speedup
Face and graph matcher • Graph matcher – Implemented on DSP to test out core. – FPGA version expected to show significant speed-up – Implement on CBV
Conclusions • DSP core built on PII • CBV processor defined and now being implemented on PII • Should fit with FAR development later
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