Accuracy Considerations in RC Extraction for STA Aya Keller, Igor - PowerPoint PPT Presentation

Accuracy Considerations in RC Extraction for STA Aya Keller, Igor Keller TAU 2019 Monterey March, 19 1

Motivation • Design trends: • Finfet era: faster cells, higher logic density, clocks scale down fast • Size grew significantly: 10 9 -instance designs are here! • Higher process variations: many process corners, often >100 • Requirements for modern STA: • High capacity and performance • Required accuracy: path delay within 2% of Spice • Waveform Aware Simulation-based delay calculation is a MUST current source models, waveforms efficient RC Reduction Fast and accurate ODE solvers     E x Ax BI ( t , v , ) V 0  V i v Cx 2 2

Motivation, cont. • Shrinking geometries lead to higher resistance and capacitance of wires 20nm higher • Good old times of C eff +TLU delay calculation are over! R, C • Wire delays scale down slower than cell delays IMAC’2017 7nm 3 3

Motivation, cont. • Many sources of inaccuracy in STA Delay Calculation ~3-4% • Is Spice an ultimate reference for delay? IR drop 3-8% ~5-10% Process Variations • Not really, uses many assumptions ~5-10% Crosstalk • Wire has a continuous though non-uniform Focus 5-10% RC Extraction 1-2% Library Characterization resistance and capacitance 1-2% Model extraction from Silicon • RC extraction replaces it with lumped R’s and C’s + • Lumping: spatial discretization 1-5% Spice Reference Error • Effects of spatial discretization on STA accuracy is Total Error vs Silicon >25% not well studied • Goal of this work RC Extraction => Spatial discretization 4

Problem Formulation N segments • Uniform wire, far-end cap • Driver: step voltage source C, R kC • Target: far-end voltage response u(t) ~ • Split into N equal segments • Approximate each with Π -model R/N C/N, R/N • Build N-link RC chain Lump C/2N C/2N • Goal: accuracy of far-end response vs N R/N R/N R/N R/N kC C/N C/N C/N C/2N ~ u(t) 5 5

Discretized Problem, Numerical Solution R/N R/N R/N R/N N 1 N-1 2 kC C/N C/N C/N C/2N u(t) ~ 6 [time]=R*C 6 6

Continuous Problem, Analytical Solution C, R ~ u(t) x 1 0 [time]=R*C Solution: 0<x<1: t=0: boundary conditions 7 7

Errors of Temporal Discretization • Numerical solution of ODEs has errors due to temporal discretization • Needs to be much smaller than spatial discretization • Errors depends on the method • Backward/Forward Euler: O(h) • Trapezoidal : O(h 2 ) Backward Euler analytical solution Trapezoidal Forward Euler 8 8

Accuracy of Wire Delay and Slew (k=0) 9 9

Voltage Responses at Far End 10 10

Results Delay, slew and relative errors for different far-end load and N Time unit = R*C 11 11

Conclusions, Future Work • Spatial discretization in RC extraction may cause large errors • We quantified errors of wire delay and slew for several far-end loads • Used analytical solution to ensure time discretization has negligible error • We demonstrated that number of segments needs to be larger than 2 for wire delay error < 2% • Is important for wire-delay dominated paths • Future work: • include crosstalk • more complex wire topologies • non-uniform wire widths and spacing 12 12