Accuracy Considerations in RC Extraction for STA Aya Keller, Igor - - PowerPoint PPT Presentation

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Accuracy Considerations in RC Extraction for STA

Aya Keller, Igor Keller TAU 2019 Monterey March, 19

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Motivation

• Design trends:
• Finfet era: faster cells, higher logic density, clocks scale down

fast

• Size grew significantly: 109-instance designs are here!
• Higher process variations: many process corners, often >100
• Requirements for modern STA:
• High capacity and performance
• Required accuracy: path delay within 2% of Spice
• Waveform Aware Simulation-based delay calculation is a

MUST

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Vi

V0

current source models, waveforms

Cx v v t BI Ax x E    ) , , (  

Fast and accurate ODE solvers efficient RC Reduction

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Motivation, cont.

• Shrinking geometries lead to higher resistance and

capacitance of wires

• Good old times of Ceff+TLU delay calculation are over!
• Wire delays scale down slower than cell delays

3 IMAC’2017

20nm 7nm

higher R, C

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Motivation, cont.

• Many sources of inaccuracy in STA
• Is Spice an ultimate reference for delay?
• Not really, uses many assumptions
• Wire has a continuous though non-uniform

resistance and capacitance

• RC extraction replaces it with lumped R’s and C’s
• Lumping: spatial discretization
• Effects of spatial discretization on STA accuracy is

not well studied

• Goal of this work

1-2% 1-2% 5-10% ~5-10% ~5-10% Delay Calculation 3-8% ~3-4% IR drop Process Variations Crosstalk RC Extraction Library Characterization Model extraction from Silicon

+

1-5% Spice Reference Error >25% Total Error vs Silicon

Focus RC Extraction => Spatial discretization

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Problem Formulation

• Uniform wire, far-end cap
• Driver: step voltage source
• Target: far-end voltage response
• Split into N equal segments
• Approximate each with Π-model
• Build N-link RC chain
• Goal: accuracy of far-end

response vs N

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C/N, R/N

N segments

R/N

C/2N C/2N

Lump C, R

kC

~

u(t)

kC

~

u(t)

C/N C/N C/N C/2N

R/N R/N R/N R/N

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Discretized Problem, Numerical Solution

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kC

~

u(t)

N N-1 2 1

C/N C/N C/N C/2N

R/N R/N R/N R/N

[time]=R*C

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Continuous Problem, Analytical Solution

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C, R

~

u(t) x 1 0<x<1: t=0:

boundary conditions

Solution:

[time]=R*C

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Errors of Temporal Discretization

• Numerical solution of ODEs has errors due to temporal discretization
• Needs to be much smaller than spatial discretization
• Errors depends on the method
• Backward/Forward Euler: O(h)
• Trapezoidal: O(h2)

8 Forward Euler Backward Euler Trapezoidal

analytical solution

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Accuracy of Wire Delay and Slew (k=0)

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Voltage Responses at Far End

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Results

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Delay, slew and relative errors for different far-end load and N Time unit = R*C

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Conclusions, Future Work

• Spatial discretization in RC extraction may cause large errors
• We quantified errors of wire delay and slew for several far-end loads
• Used analytical solution to ensure time discretization has negligible error
• We demonstrated that number of segments needs to be larger than 2 for wire

delay error < 2%

• Is important for wire-delay dominated paths
• Future work:
• include crosstalk
• more complex wire topologies
• non-uniform wire widths and spacing

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