A Pulse-Driven VCO with Enhanced Efficiency Aravind Tharayil - - PowerPoint PPT Presentation

A Pulse-Driven VCO with Enhanced Efficiency

Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, and Akira Matsuzawa

Matsuzawa & Okada Lab.

b.

y

Matsuzawa & Okada Lab.

b.

y

Tokyo Institute of Technology, Japan

1

Contents

! Motivation ! Evaluation of VCO Topologies ! Effects of MOSFET Sizing ! Pulse VCO ! Measurement Results ! Conclusion

2

Motivation

VCO for next generation wireless devices

Low power TRx is required for next gen portable devices ! High purity ! High efficiency VCO – A major power consumer in TRx.

[H. Darabi, JSSC 2011]

RX 62% VCO 38% ! Small area 30mA 19mA

3

Evaluation of VCO Topologies

[M. Garampazzi, ESSCIRC 2014] [A. Hajmiri, JSSC 1998]

Generalized expression for phase noise Figure of Merit (FoM) facilitates fair VCO comparison

Assuming 100% efficiency and noise free active elements:

FoMMAX depends only on Q

4

Evaluation of VCO Topologies

ENF = FoMMAX – FoM

Excess Noise Factor (ENF)

[M. Garampazzi, ESSCIRC 2014]

ENF depends only on topology For high performance VCOs:

• 1. Increase power efficiency
• 2. Decrease noise sensitivity

5

High Efficiency VCOs

Class-C Class-D Class-F High Current efficiency High Voltage Efficiency

VP VN VDD M1 M2 M3 CTail VTail Vgbias VP VN VDD LDO M1 M2 M1 M2 VP VN KM VDD VDD M3 CTail VTail

[P. Andreani, JSSC 2008] [L. Fanori, JSSC 2013] [M. Babaie, JSSC 2013]

Low Noise Sensitivity

6

High Efficiency VCOs

✓ High ηI

" Good candidate for practical high efficiency VCO.

✗ Low ηV

" Supply pushing. " Loading effects. " Reliability issues. ηP = ηI × ηV ηI : Current efficiecny ηV : Voltage efficiecny

✗ High !i

" Additional area. " Limited improvement.

[M. Babaie , JSSC 2013] [A. Visweswaran, ISSCC 2012] [L. Fanori, JSSC 2013] [P. Andreani, JSSC 2008]

7

Tackling Efficiency: Class-C VCO

[A. Mazzanti and P. Andreani, JSSC 2008]

Vds Vgbais Vth VDD

ϖ

• ϖ

−Φ Φ

Vds Vgs VDD Ids Ids Ibias

ϖ

• ϖ

(a) (b)

• ϖ 2

ϖ 2

• ϖ 2

ϖ 2

Vgs-Vth At

Class-C achieves high current efficiency

8

!!"# = !!! − (!!" − !!") !

Efficiency and MOS sizing

[K. Okada, VLSI Circuits 2009]

Large MOS required for better efficiency

VDS VDD VTH IDS1 Imax1 Imax2 IDS2 ϖ

• ϖ

ϖ

• ϖ

2 2

−Φ2 −Φ2

VGS Small MOS Large MOS

−Φ1 Φ1

For high efficiency # Large Amax # Small VGS # Small conduction angle

9

Noise Contribution of MOSFET

Low conduction angles increases the noise from MOSFETs

5 10 15 20 4

ϖ

2

ϖ

Conduction Angle [rad] MOS Noise [dB]

10

VP VN M1 M2 Cgs,M1 Cgs,M2 Vgbias VDD Behavior of Cgs Cgs VTail CTail CGS CL CH CT VGS VTH VDS+TH

Large MOS - Secondary Effects

Tank capacitance is susceptive to VGS variations (cut-off) (saturation)

11 VP VN VDD Time Domain Analysis CGS Bias

• R

t t

VDS VGS f V δf ϖ

• ϖ

2ϖ

• 2ϖ

VTH VDD CGS CH CT CL VGS ∆C2 ∆C1 CGS f0-Δf2 f0-Δf1 ∆VGS2 ∆VGS1

AM-PM Conversion in Class-C VCO

Variations in CGS translates to phase noise

12

Effects of MOS sizing

Lowering VGS worsens the phase noise

• 0.3

0.0 0.3 0.6

• 115
• 110
• 105
• 100

Phase Noise [dBc/Hz] Vgbias[V]

• 95
• 90

simulaon including MOS sizing effects excluding MOS sizing effects

13

Pulse Drive: The Concept

VDD Vgbias Vgs-Vth t t

ϖ

• ϖ
• ϖ

Ids Vds V

2

ϖ 2

Φ

• Φ

At

Conduction angle is varied by varying gate voltage

14

t VDD t

ϖ

• ϖ
• ϖ

Vds

2

ϖ 2

Φ −Φ

V Vgs At Ids

Pulse Drive: The Concept

Conduction angle is controlled by pulse width

15

5 10 15 20 4

ϖ

2

ϖ

Conduction Angle [rad] MOS Noise [dB]

Noise Contribution of MOSFET

MOSFET noise is kept under limit Class-C Pulse VCO

16

Theoretical Limit of ENF

Pulse VCO achieves ~5dB improvement in ENF when compared to class-C topology

4

ϖ

2

ϖ

Class-C Pulse-Drive

Conduction Angle [rad] ENF [dB] 5 10 15 20

17 VP VN VDD

Time Domain Analysis

CGS

Pulse Drive

• R

CGS CH CT CL VGS

t t

VDS VGS VTH VDD CGS V f f0

t

ϖ

• ϖ

2ϖ

• 2ϖ

CL CT ∆VGS2 ∆VGS1 f0-Δf f0-Δf

Analysis: AM-PM Conversion

AM-PM translation is minimized.

18

Proposed Circuit Schematic

VDD IB M1 M2 MTail CTail conduction angle control Amplitude regenerator VP VTail VN Cb Rb VDD IB Cb Rb VDD Vbp Vbn

19

θ

ϖ

• Cond. Angle

Control Amplitude Regeneration

Class-AB Class-B Induced Class-C

IB Sense Cb Rb Mb NB Vbp Vp Vbp VDD ATank VTH VDD VDD VInit V(NB) θ

t

ϖ

Pulse Drive: Startup

High robustness

20

θ

ϖ

• Cond. Angle

Control Amplitude Regeneration

Class-AB Class-B Induced Class-C

IB Sense Cb Rb Mb NB Vbp Vp Vbp VDD ATank VTH VDD VDD VInit V(NB) θ

t

ϖ

Pulse Drive: Startup Contd.

21

θ

ϖ

• Cond. Angle

Control Amplitude Regeneration

Class-AB Class-B Induced Class-C

IB Sense Cb Rb Mb NB Vbp Vp Vbp VDD ATank VTH VDD VDD VInit V(NB) θ

t

ϖ

Pulse Drive: Steady State

High Efficiency

22

Chip Micrograph

Proposed

Vgbias M1 M2 VP VTail CTail VN VDD M1 M2 VP Pulse Drive Pulse Drive VTail CTail VN VDD

Reference VCO Pulse Drive

62 45

250 500 250 500

23

Measurement Results

• 50
• 60
• 70
• 80
• 90
• 100
• 110
• 120
• 130
• 140
• 150

1k 10k 100k 1M 10M Reference VCO Pdc = 2.54mW FoM = -190dBc/Hz This work Pdc = 2.05mW FoM = -192dBc/Hz

• Current implementation limits the maximum achievable frequency.
• Spikes in the frequency spectrum can be removed by circuit techniques.

24

Performance Comparison

CMOS Process Frequency [GHz] Phase Noise [dBc/Hz] Pdc [mW] FoM [dBc/Hz]

[1] JSSC2008 130nm 4.9

• 130@1MHz

1.30

• 196

[2] VLSI2009 180nm 4.5

• 109@1MHz

0.16

• 190

[3] JSSC2013 180nm 4.84

• 125@1MHz

3.40

• 193

[4] ESSCIRC2011 90nm 5.1

• 120@1MHz

0.86

• 192

[5] JSSC2013 65nm 3.7

• 142@3MHz

15.0

• 192

[6] JSSC2013 65nm 4.8

• 144@10Mhz

4.00

• 191

This Work 180nm 3.6

• 124@1MHz

2.05

• 192

[1] A. Mazzanti and P. Andreani, JSSC 2008. [2] K. Okada et al., VLSI 2009. [3] W. Deng et al., JSSC 2013. [4] M. Tohidian et al., ESSCIRC 2011. [5] M. Babaie et al., JSSC 2013. [6] L. Fanori et al., JSSC 2008

25

Conclusion

# Techniques for high performance, low power VCOs are briefly introduced. # A performance limiting factor in class-C VCO is identified. # Pulse Bias technique is proposed, which can achieve very high efficiency. # A VCO working on the proposed pulse-bias scheme is presented along with measurement results.

26

APPENDIX

27

Noise from the additional MOS

Delay introduced by the inverter is within safe ISF region.

VDD VDD CP CCC VP VN LP CP LP Pulse Generator

τ

VDS IDS ISF T1

Delay becomes trivial in advanced processes.

28

Noise Contribution

Noise introduced by the driver circuitry is small.

Components Noise Contribution (%)

10 20 30 40 MCC Tank MTAIL RBIAS MBIAS Misc.

MCC MCC N1 N2 P_Drive P_Drive VTail VP Tank VN MTail CTail MBIAS

IB Cb RBIAS Mb N1 Vp VDD

29

Simulated Waveforms (1)

• 1.E-03

0.E+00 1.E-03 2.E-03 3.E-03 4.E-03 5.E-03 6.E-03 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 3.85E-07 3.85E-07 3.85E-07 3.85E-07 3.85E-07 Current (A) Voltage (V) Time (s)

30

Simulated Waveforms (2)