Class-C VCO with Dynamic Bias Control Circuits Teerachot - PowerPoint PPT Presentation

A Swing-Enhanced Current-Reuse Class-C VCO with Dynamic Bias Control Circuits Teerachot Siriburanon, Wei Deng, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan b. b. Matsuzawa Matsuzawa & Okada Lab. & Okada Lab. y y

Conventional Class of LC-VCOs Current-Reuse NMOS LC-VCO CMOS LC-VCO LC-VCO [ S.-J. Tun, et al. , ISSCC 2005] Out- Out+ VDD • • Conduct current half • Better reliability Good phase noise • period 2x amplitude in performance at • Inherit same benefits current-limited regime moderate power of CMOS VCO (6dB FoM reduction) 2

Class-C VCO  Class-C VCO [ A. Mazzanti, and P. Andreani, ISSCC 2008] - Biasing NMOS cross-coupled MOSFETs in class-C operation V gbias - More efficient MOS current generation With same power budget, phase noise achieves a significant improvement (3.9dB reduction in FoM) 3

LC-VCO Topologies Better FoM performance Current-Reuse VCO NMOS VCO CMOS VCO (asymmetric wave) 3.9dB Class-C CMOS Class-C NMOS (JSSC 2013) (ISSCC 2008) Class-C - startup issue - startup issue Current Reuse with Dynamic Feedback Class-C Bias Circuits (ESSCIRC 2011) Possible? Lower current consumption 4

Proposed Current-Reuse Class-C VCO A t A t V cm V cm V ctrl V out- V out+ I REF M3 V bias M1 M2 M4 I REF V DD • Dynamic Bias Control Circuits for Class-C operation – Reliable startup & enhance oscillation swing 5

Performance Comparison Freq./Offset Phase Power FoM Topology Freq. Noise [mW] [dBc/Hz] [GHz/MHz] [dBc/Hz] ISSCC’13 Class-D 3.3/5 -144 6 -190 ISSCC’10 CMOS 3/1 -114 0.7 -187 ISSCC’12 CMOS 6.8/2 -123 9 -185 Current- ISSCC’05 2.0/1 -123 1 -189 Reuse Class-C Proposed 2.4 -189 Current- 4.6/1 -119 Reuse • The proposed work achieves low phase noise as well as low power consumption 6