A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a - - PowerPoint PPT Presentation

a new self aligned quantum well mosfet architecture
SMART_READER_LITE
LIVE PREVIEW

A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a - - PowerPoint PPT Presentation

A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process Jianqiang Lin, Xin Zhao, Tao Yu, Dimitri A. Antoniadis, and Jess A. del Alamo Microsystems Technology Laboratories, MIT December 10, 2013


slide-1
SLIDE 1

A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight-Pitch Process

Jianqiang Lin, Xin Zhao, Tao Yu, Dimitri A. Antoniadis, and Jesús A. del Alamo

Microsystems Technology Laboratories, MIT December 10, 2013 Sponsors: FCRP-MSD Center, Intel, E3S STC, MIT SMA and SMART

1

slide-2
SLIDE 2

Motivation

  • Superior electron transport properties in InAs channel

2

[J. del Alamo, Nature 2011]

InAs HEMTs Strained Si VDS=0.5 V Si

VDS=1.1-1.3 V

2

slide-3
SLIDE 3

InGaAs MOSFET evolution

3

[del Alamo, ESSDERC 2013] (Kim, IEDM 2012)

Performance Fabrication and Scaling

slide-4
SLIDE 4

InGaAs MOSFET evolution

4

[del Alamo, ESSDERC 2013] (Kim, IEDM 2012)

Performance Fabrication and Scaling

(This work)

slide-5
SLIDE 5

New InGaAs MOSFET with self-aligned LEDGE

  • Bottleneck to ON current is Rsd
  • Introduction of highly conductive “LEDGE”

– n+ region linking metal contact and channel

5

slide-6
SLIDE 6

Process integration

6

Key features: Wet-etch free / Lift-off free / Au free

Ohmic/Oxide deposition* Gate opening 3-step gate recess ALD deposition Gate metal Pad formation

slide-7
SLIDE 7

Composite W/Mo contact

7

  • Without W: Long undercut of Mo due to oxidation

– Limits S/D metal spacing

  • With W: No Mo oxidation

[Lin, IEDM 2012] This work

Air void

s

slide-8
SLIDE 8

3-step gate recess process

8

Process enables precise control of: tch / Lledge / tledge

CF4+O2 RIE * Digital etch*:

O2 plasma + H2SO4

Cl-based RIE

*[Waldron, IEDM 2007]

tch Lledge tledge Lg

*[Lin, EDL submitted]

slide-9
SLIDE 9

Semiconductor surface after recess

9

5 nm Scanning area: 2x2 m2

Only wet cleaning (no etching) Additional cap dry etch (~ 20 nm) + 4 cycle digital etch RMS = 0.12 nm RMS = 0.21 nm

slide-10
SLIDE 10

Structure design: Ledge

10

Short Ledge Long Ledge

slide-11
SLIDE 11

Structure design: Ledge

11

  • Surface channel: In0.7Ga0.3As / InAs / In0.7Ga0.3As = 1/2/5 nm
  • High-k: HfO2 , thickness =2.5 nm (EOT~0.5 nm)

Short Ledge Long Ledge

slide-12
SLIDE 12

Output and gm characteristics for Lg = 70 nm

12

  • Ron = 220 m for Lledge= 5 nm
  • Record gm,max = 2.7 mS/m at Vds= 0.5 V for Lledge= 5 nm
  • 0.4 -0.2 0.0 0.2 0.4

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Lledge=5 nm, 2.7 mS/m Lledge=70 nm, 1.9 mS/m

Vds= 0.5 V

gm (mS/m) Vgs (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0

Lledge= 70 nm Lledge= 5 nm

Vgs-Vt = 0 to 0.5 V in 0.1 V step

Id (mA/m) Vds (V)

slide-13
SLIDE 13

Subthreshold characteristics

13

  • Ig < 10 pA/µm over entire voltage range

– Further EOT scaling possible Lledge=5 nm

  • 0.2

0.0 0.2 0.4 10

  • 9

10

  • 7

10

  • 5

10

  • 3

Vds=0.05 V Smin=108 mV/dec Vds=0.5 V Smin=138 mV/dec

Id (A/m) Vgs (V)

DIBL=249 mV/V

  • 0.4
  • 0.2

0.0 0.2 10

  • 9

10

  • 7

10

  • 5

10

  • 3

Vds=0.5 V Smin=94 mV/dec Vds=0.05 V Smin=90 mV/dec DIBL=130 mV/V

Id (A/m) Vgs (V)

Lledge=70 nm

slide-14
SLIDE 14

Subthreshold characteristics

14

  • Ig < 10 pA/µm over entire voltage range

– Further EOT scaling possible Lledge=5 nm

  • 0.2

0.0 0.2 0.4 10

  • 9

10

  • 7

10

  • 5

10

  • 3

Vds=0.05 V Smin=108 mV/dec Vds=0.5 V Smin=138 mV/dec

Id (A/m) Vgs (V)

DIBL=249 mV/V

Flattening tail at high

Vds

  • 0.4
  • 0.2

0.0 0.2 10

  • 9

10

  • 7

10

  • 5

10

  • 3

Vds=0.5 V Smin=94 mV/dec Vds=0.05 V Smin=90 mV/dec DIBL=130 mV/V

Id (A/m) Vgs (V)

Lledge=70 nm

slide-15
SLIDE 15

Lg= 20 nm InAs QW-MOSFET with Lledge= 5 nm

15

  • Smallest functional III-V MOSFET with tight

contact spacing

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0

Lg=20 nm Ron=224 m 0.4 V

Id (mA/m) Vds (V)

Vgs-Vt= 0.5 V

slide-16
SLIDE 16

Parasitic resistance analysis

16

  • For short ledge devices, major Rsd contribution

from Rcont and Rbar

Pad W/Mo n+ Cap Channel Buffer Rprobe= 5 m Rmetal= 5 m Rcont= 50 m Rledge~ 1 m/nm Rbar= 40 m Gate

200 400 200 300 400 500

Lledge=70 nm, Rsd =302 m

Ron (m) Lg (nm)

Lledge=5 nm, Rsd =206 m

slide-17
SLIDE 17

Benchmark: I on

17

  • Record Ion = 410 A/m at Lg=70 nm for Lledge=70 nm

50 100 150 200 100 200 300 400 500

InGaAs FETs

Ion (A/m) Lg (nm)

Ioff=100 nA/m, Vdd=0.5 V

Planar Trigate MIT HEMT MIT MOSFET 2012 This work(Lledge=70 nm) This work(Lledge=5 nm)

* [Kim and del Alamo, T-ED 2008]

*

slide-18
SLIDE 18

Benchmark: gm,max vs. S

18

  • Short ledge MOSFETs show record gm,max
  • Long ledge MOSFETs match record S

[Radosavljevic, IEDM 2011]

100 200 300 400 0.0 0.5 1.0 1.5 2.0 2.5 3.0

InGaAs FETs Planar Trigate MIT HEMT Teledyne/MIT HEMT MIT MOSFET 2012 This work(Lledge=70nm) This work(Lledge=5 nm)

Vds= 0.5 V Lg70 nm gm-max (mS/m) Smin (mV/dec)

slide-19
SLIDE 19

Impact of ledge on off-state leakage (Long MOSFETs)

19

Flattening tail at high Vds

  • Short ledge leads to high Ioff
  • Strong Vds dependence

Lg= 200 nm, Lledge = 70 nm Lg= 500 nm, Lledge = 5 nm

  • 0.4 -0.2 0.0 0.2

10

  • 14

10

  • 12

10

  • 10

10

  • 8

10

  • 6

10

  • 4

Id

Vgs (V)

Ig

Vds=0.1 to 0.6 V

  • 0.2 0.0 0.2 0.4

10

  • 14

10

  • 12

10

  • 10

10

  • 8

10

  • 6

10

  • 4

Id Id or Ig (A/m)

Vgs (V)

Ig

Vds=0.1 to 0.6 V

slide-20
SLIDE 20

Off-state leakage: Temperature dependence

20

  • GIDL (gate-induced drain leakage) signature
  • 0.4 -0.2 0.0 0.2

10

  • 14

10

  • 12

10

  • 10

10

  • 8

10

  • 6

10

  • 4

Id Id or Ig (A/m)

Vgs (V)

300K Ig

Vds=0.1 to 0.6 V

  • 0.4 -0.2 0.0 0.2

10

  • 14

10

  • 12

10

  • 10

10

  • 8

10

  • 6

10

  • 4

Id

Vgs (V)

150K Ig

  • 0.4 -0.2 0.0 0.2

10

  • 14

10

  • 12

10

  • 10

10

  • 8

10

  • 6

10

  • 4

Id

Vgs (V)

77K Ig

Lg= 500 nm, Lledge = 5 nm

slide-21
SLIDE 21

Off-state leakage follows BTBT signature

21

  • Is follows BTBT dependence on Vdg and Eg

1.0 1.2 1.4

10

  • 12

10

  • 10

10

  • 8

Vds= 0.6 V Vds= 0.5 V Vds= 0.4 V

|Is| ( A/m) Vdg

  • 1 (V
  • 1)

T=77 K 0.44 0.48 0.52

10

  • 9

10

  • 8

300K 150K

|Is| (A/m) Eg

3/2 ( eV 3/2)

77K Vds=0.6 V Vgs= -0.4 V

~ exp

slide-22
SLIDE 22

GIDL simulations

22

BTBT Ec Ev

S D G

TCAD simulation of BTBT rate based on nonlocal path BTBT model:

n+ contact Oxide InGaAs InAs InGaAs InP InAlAs 2 nm Gate

slide-23
SLIDE 23

Conclusions

23

  • Novel self-aligned III-V QW-MOSFETs:

– Lift-off free, wet-etch free, and Au free in front end process – Design and fabrication of critical S/D ledge – Tight metal contact spacing – Scaled channel thickness, barrier thickness and gate length

  • Record results demonstrated:

– gm,max = 2.7 mS/m in Lledge = 5 nm – Ion = 410 A/m in Lledge = 70 nm

  • Characteristic GIDL signature observed