A Highly-dense Mixed Grained Reconfigurable Architecture with - - PowerPoint PPT Presentation
A Highly-dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-switch 1 Junshi Hotate 1,6 Takashi Kishimoto 1,6 Toshiki Higashi 1,6 Hiroyuki Ochi 1,6 Ryutaro Doi 2,6 Munehiro Tada 3,6 Tadahiko Sugibayashi 3,6
Junshi Hotate1,6 Takashi Kishimoto1,6 Toshiki Higashi1,6 Hiroyuki Ochi1,6 Ryutaro Doi2,6 Munehiro Tada3,6 Tadahiko Sugibayashi3,6 Kazutoshi Wakabayashi3,6 Hidetoshi Onodera4,6 Yukio Mitsuyama5,6 Masanori Hashimoto2,6
1Ritsumeikan University 2Osaka University 3NEC Corporation 4Kyoto University 5Kochi University of Technology 6JST, CREST
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Conventional SRAM-based FPGA
Logic (LUT/ DSP/ Mem)
T1 T2
SRAM + MOS Switch
All in FEOL layers
FEOL layers
Proposed Architecture BEOL layers
FEOL layers
Via-Switch array
Logic (LUT/ Arith/ Mem)
T1
T2
Contributions Chip area Crossbar density Delay Energy 26X
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are replaced by Via-Switch.
set of logic resources.
T1 T2 C2 C1
Varistors Complementary atom switch
non-linear device for selecting an atom switch to be programmed non-volatile resistive RAM
①Small footprint ②Low resistance(on-R 200Ω) ③Low parasitic capacitance ④Multi-fanout support (0.14fF) (6F×3F) <Features>
Via-switch is a non-volatile and re-programmable switch. T1 and T2 are connected and disconnected.
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Array structure Unit tile
The proposed architecture is a homogeneous array of unit tiles
The unit tile consists of four crossbar blocks (XBs), eight fine-grained logic blocks (LBs) and a coarse-grained arithmetic block (AB) or memory block (MB).
LB LB LB LB LB LB LB LB XB XB XB XB AB
MB
4
LUT
Arith
Mem
To/From West
Crossbar
Via-switch(6F×3F)
To/From East
Each wire segment is a bidirectional interconnect
Arithmetic Block
16 16 16 32 17 33 34 34
Logic Block
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XB LB AB
BEOL layers
FEOL layers
Target Architecture AB LB Unit tile array size FGRA ― 512 8×8 (512LB) MGRA (proposed) 14 76 4×4 (16AB+128LB)
We implemented a design “CConv”, a front-end circuit for image sensor including RGB-YUV conversion
Required logic resources for “CConv”
C CWB RTL
Technology mapping
Netlist Placement Routing <Design Flow> <Target Design>
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Circuit simulation result at 0.5V operation using a circuit model of 91×44 crossbar with the equivalent circuit model of the via-switch Comparison of the array area needed for implementing “CConv”
(1)Array Area
Architecture Track BEOL FEOL area area Tile area Array size Array area FGRA unidir. 68 441kF2 87kF2 5508μm2 8×8 352512μm2 MGRA bidir. 44 308kF2 426kF2 5319μm2 4×4 85108μm2
(2)Delay and Energy
Energy [pJ] Distance (# of XBs) Delay [ns]
This improvement can contribute to filling the gap between FPGA and ASIC.
Distance (# of XBs)
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