Reconfigurable Computing Computing Reconfigurable Design and implementation implementation Design and Chapter 4.2 4.2 Chapter Prof. Dr.- -Ing. Jürgen Teich Ing. Jürgen Teich Prof. Dr. Lehrstuhl für Hardware- -Software Software- -Co Co- -Design Design Lehrstuhl für Hardware Reconfigurable Computing
Brief tour through logic synthesis Brief tour through logic synthesis 2 Reconfigurable Computing
Logic synthesis - - Goal Goal Logic synthesis � A digital system consists of combinatorial parts separated by memory elements The goal of the logic synthesis is � to provide an implementation of a digital system for a given platform or for a given target library � FPGA-Goal: Generation of configuration data digital system � The implementation must be optimized according to factors such as area, delay, power consumption, testability, etc... Reconfigurable Computing 3
Logic synthesis - - Two Two- -level level- -logic logic Logic synthesis Logic synthesis is usually divided into two parts: X1 � Two-level logic synthesis: * � designs represented in two-level logic X2 (sum of product-terms, the sums are F * X3 implemented on the first level and the + X2 product on the second level) * � Advantages: X4 � Natural representation of Boolean * functions X3 � Well understood and easy Two-level logic manipulation � Drawbacks: not representative for the logic complexity. Therefore, bad estimator of complexity during logic optimization � Initially developed for PALs and PLAs Reconfigurable Computing 4
Logic synthesis - - Multi Multi- -level level- -logic logic Logic synthesis � Multi-level logic synthesis: targets multi-level (many Boolean function F2 X1 on the path from the inputs to the outputs) X2 � Advantages: X3 F1 � Smaller, faster, less power in most cases X2 � Drawbacks: X4 � Difficult to manipulate X6 F3 � Few manipulation algorithms exist X5 � Appropriate for mask-programmable or field programmable devices X5 Multi-level logic � Multi-level will be therefore considered in this course Reconfigurable Computing 5
Logic synthesis - - Boolean Networks Boolean Networks Logic synthesis Multi-level logic is usually represen- ted using Boolean networks (BN). A BN is a directed acyclic graph (DAG) in which � a node represents an arbitrary Boolean function � An edge represents the (data) dependency between nodes In order to efficiently manipulate a Boolean network, viable represen- tation of nodes is necessary. The important factors considered are: � memory efficiency � correlation with the final representation Reconfigurable Computing 6
Logic synthesis - - Node representation Node representation Logic synthesis The choices usually made for node representation are: � Sum-Of-Products (SOP) � Factored Form (FF) � Binary Decision Diagram (BDD) � Sum-Of-Product: Sum of product terms � Factored form (FF): Defined recursively as follows: � (FF = product) or (FF = sum). � (product = literal) or (product = FF1*FF2). � (sum = literal) or (sum = FF1+FF2). + + Example: is a product of the factored forms c ( a b ( d e )) + + c and , which in turn is a sum of the factored a b ( d e ) + a b ( d e ) forms and Reconfigurable Computing 7
Logic synthesis - - Node representation Node representation Logic synthesis � Binary Decision Diagram (BDD): A BDD is a rooted DAG with two kinds of nodes: � Variable nodes : A variable node v is a non-terminal node with the following attributes: � index(v) ∈ {1,…,n} (i defines a variable xi) � Two children low(v) and high(v) � Constant nodes: A constant node v is a terminal node with value(v) ∈ {0, 1} � The nodes are ordered from the root to the terminal nodes. � For each non-terminal v, if low(v) is non terminal, then index(low(v)) < index(v) � Similarly, if high(v) is non-terminal, then index(high(v)) < index(v) Reconfigurable Computing 8
Logic synthesis - - Node representation Node representation Logic synthesis � Correspondence between a BDD with root v and a Boolean function � The root represents the Boolean function f v � If v is terminal, then f v = value(v) � If v is a non terminal node with index i, the Shannon expansion theorem is used: = + f x f x f v i low ( v ) i high ( v ) � The value of f v for a given assignment is obtained by traversing the graph from the root to the terminal according to the assignment values � The figure aside shows the optimal-BDD representation of the function = + + f abc b d cd Reconfigurable Computing 9
Logic synthesis - - Node manipulation Node manipulation Logic synthesis � Given a suitable node representation, operations are performed on the Boolean network. The goal is the generation of an equivalent and cost effective simplified function. � The operations usually applied for the reduction of Boolean networks are: � Decomposition: Replace a Boolean expression with a collection of new expressions. A Boolean function f(X) is decomposable if we can find a function g(X) such that f(X) = f’(g(X), X) = + + + Example: f abc abd a c d b c d 12 literals = + + + = + + + f ab ( c d ) ( a b ) c d ab ( c d ) ab ( c d ) Decomp.: 8 literals � Extraction: Use to identify common intermediate sub-functions from a set of given functions. = + + = + Example: can be rewritten as f ( a bc ) d e , g ( a bc ) e = + = = + f xd e , g x e with x ( a bc ) Reconfigurable Computing 10
Logic synthesis - - Node manipulation Node manipulation Logic synthesis � Factoring: Transformation of SOP-expressions in factored form = + + + + Example: f ac ad bc bd e can be rewritten as = + + + f ( a b )( c d ) e � Substitution: Replace an expression e within a function f with the value of an equivalent expression g(X) = e = + + Example: f ( a bc )( d e ) can be rewritten as = + = + f g ( d e ) with g a bc � Collapsing or Elimination: Reverse operation to substitution. It is use to eliminate levels in order to meet timing constraints = + = + Example: f ga g b with g c d will be replaced by = + + f ac ad b c d Reconfigurable Computing 11
Logic synthesis - - LUT LUT- -Technology mapping Technology mapping Logic synthesis � Technology mapping binds the optimized nodes of the Boolean network to the target device library. � In the FPGA case, library elements are LUTs. Therefore, this process is called LUT-based Technology mapping. � LUT-Based technology mapping is an optimization process whose goal is usually: � Minimizing the number of LUT used (device area) � Minimizing the signal delay (Speed) � Optimizing routability, minimizing power (very few work) � In this chapter, we will study two LUT-technology mapping algorithms. � The chortle-crf for area minimization � The FlowMap for delay minimization Reconfigurable Computing 12
Logic synthesis - - LUT LUT- -Technology mapping Technology mapping – – Logic synthesis definitions definitions Given a Boolean network: � A primary input (PI) node is a node with no predecessor. A primary output (PO) is a node which has no successor. � The level of a node is the length of the longest path from the primary input to that node. � The depth of a graph is the largest level of a node in the graph. � For a node v, input(v) is defined as the set of nodes which are fan-in of. v A Boolean network is K-Bounded, if input(v) ≤ K for all � nodes in the graph. Reconfigurable Computing 13
Logic synthesis - - LUT LUT- -Technology mapping Technology mapping – – Logic synthesis definitions definitions � A Cone C v at a node v is the tree with root which spans from v v to the primary inputs. � A Cone C v at a node v is K-feasible if: � input(v) ≤ C v � Any path connecting a node A K-feasible Cone at v in C v and v lies entirely in v � The LUT-technology mapping problem can be defined as the problem of covering a Boolean network with a set of K- feasible cones. Graph covering with cones LUT Mapping Reconfigurable Computing 14
Logic synthesis - - LUT LUT- -Techmap Techmap- -The Chortle The Chortle- -crf crf Logic synthesis algorithm algorithm � Developed by Francis et al., University of Toronto in 1991. � bin packing approach which traverses the nodes from the primary inputs (PIs) to the primary outputs (POs) � At each node, the best circuit implementing the K-feasible cone at that node is searched for. � The two main goals are: � Minimizing the number of LUTs and therefore the device area. � Minimizing the number of used pins at the output LUTs. � Approach: At each node, construct a tree of LUTs � that implements the function of the fan-in LUT � that implements the decomposition of the node Reconfigurable Computing 15
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