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Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip Hiroto Yasuura Kazuaki Murakami System LSI Research Center (SLRC) Kyushu University E-mail: yasuura@slrc.kyushu-u.ac.jp Outline Outline


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SLIDE 1

Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip

Hiroto Yasuura Kazuaki Murakami

System LSI Research Center (SLRC) Kyushu University

E-mail: yasuura@slrc.kyushu-u.ac.jp

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SLIDE 2
  • H. Yasuura, Kyushu Univ.

MPSOC'03 2

Outline Outline

■ Background and Requirements ■ Platforms for Reconfigurable Computing

■ DRP ■ DAP/DNA

■ How to use Reconfigurable Computing in

SoC

■ SysteMorph

■ Conclusion

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SLIDE 3
  • H. Yasuura, Kyushu Univ.

MPSOC'03 3

Why Reconfigurable?

n

Cost of Production

n

Drastic increase of design and mask cost is requesting new system architectures, especially for small scale production less than 1M.

n

Customer Satisfaction

n

Various kinds of customers, each of which has different requirement and knowledge. A customized system for each user is attractive.

n

Market Oriented SoC Design

n

The direction of the market changes quickly and various new services are introduced.

n

Reliability and Security

n

Repairs and debugging on customer site.

n

Changing system configuration for security. (cryptography etc.)

n

Global Environment Problem

n

Grow out of the throwaway society.

n Views of System Designers and Users

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SLIDE 4
  • H. Yasuura, Kyushu Univ.

MPSOC'03 4

Example: Mobile Phone

n New Services

n I-mode (Internet Access: e-mail and WWW) n Built-in Digital Still Camera n Video Phone Service (MPEG-4 in NTT Foma) n Melody Calling n Music Down Load Service(MP3) n Electric Ticketing n Electric Money for Vending Machines n Simple Interface for Old People n Car Navigation Service

n Needs for a new system architecture solution

n Reconfigurable computing is a possible solution.

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SLIDE 5
  • H. Yasuura, Kyushu Univ.

MPSOC'03 5

System Level Optimization

n What

n Parameters for optimization n Goals of optimization QoS (Function, Performance,

Energy, Reliability, Security,…)

n When

n Design Stage, Compilation Stage, and Runtime

n Who

n Designers, Service Providers, and also Users

n How

n Reconfigurable Hardware Platforms n Software n Profiling and Design Optimization Techniques

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SLIDE 6
  • H. Yasuura, Kyushu Univ.

MPSOC'03 6

Runtime Runtime

SW SW HW&SW HW&SW

Compile Stage Compile Stage

HW HW

DCO EH

Codesign

SysteMorph SysteMorph

Design Stage Design Stage

SRC

DCO: Dynamic Compilation/Optimization CO: Compiler Optimization EH: Evolvable Hardware SRC: Static Reconfigurable Computing

When? What?

CO

Online Profiling & Reconfiguration Offline Profiling & Optimization

Reconfigurable Computing

Offline Profiling & Reconfiguration By K. Murakami

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SLIDE 7
  • H. Yasuura, Kyushu Univ.

MPSOC'03 7

Runtime Reconfiguration

n Dynamic: Optimization is performed…

n After SoC is shipped to the market n While SoC is used in the field

n Online: Profiling and optimization are

performed…

n In parallel with the execution of application

programs

n During idle or sleeping time

n Adaptive: Optimization is repeated…

n In the form of a feedback loop

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SLIDE 8
  • H. Yasuura, Kyushu Univ.

MPSOC'03 8

Analogy: Formula 1

The car is running in the course. The pit crew is monitoring the behavior of the car Once the pit crew finds any hints for reconfiguration, the car pits in The car is now under reconfiguration After the reconfiguration, the car returns to the course. By K. Murakami

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SLIDE 9
  • H. Yasuura, Kyushu Univ.

MPSOC'03 9

When reconfiguration is done?

Zzzzzz...

A system is not always active. Reconfiguration can be done in idle and sleep time.

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SLIDE 10
  • H. Yasuura, Kyushu Univ.

MPSOC'03 10

A Possible Business Model: OSP (Optimization Service Provider)

Optimization

OSP (Optimization

Service Provider)

Users in the field Zzzzzz...

Profile your behaviors

Pit Center

Profile your habits Profile your favorites Improve your PDA while you sleep

Configuration Data Profiled Data

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SLIDE 11
  • H. Yasuura, Kyushu Univ.

MPSOC'03 11

Customizable Mobile Phone

On-line Profiling Optimization Service Provider Improving QoS in Sleep

Sound quality Battery life Key operation New services Debugging

Out-of-Suit Optimization Your phone is evolving every battery charging!

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SLIDE 12
  • H. Yasuura, Kyushu Univ.

MPSOC'03 12

Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip

■ Background and Requirements ■ Platforms for Reconfigurable Computing

■ DRP ■ DAP/DNA

■ How to use Reconfigurable Computing in SoC

■ SysteMorph

■ Conclusion

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SLIDE 13
  • H. Yasuura, Kyushu Univ.

MPSOC'03 13

Platforms for Reconfigurable Computing ■Dynamically Reconfigurable Processor: DRP by NEC ■DAP/DNA by IP Flex ■Dynamically Reconfigurable Circuits by Sony

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SLIDE 14
  • H. Yasuura, Kyushu Univ.

MPSOC'03 14

Platforms for Reconfigurable Computing

n Granularity of Reconfiguration

n A Processor and Software n An Processor Array n Processing Elements

n ALU, Multipliers, etc.

n Logic Gates (FPGA)

n Timing of Reconfiguration

n Every Clock Cycle n Every Task Execution n Every Power-on

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SLIDE 15
  • H. Yasuura, Kyushu Univ.

MPSOC'03 15

Dynamically Reconfigurable Processor:DRP

By NEC 8DRP cores on a Chip A DRP core includes 64 PEs. STC controls PEs. 8KB 256B

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  • H. Yasuura, Kyushu Univ.

MPSOC'03 16

PE of DRP

  • 16 instructions can be

stored in the instruction memory of each PE.

  • An instruction specifies

connections and

  • peration of each

processor.

  • The STC specifies the

address of instruction.

By NEC

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SLIDE 17
  • H. Yasuura, Kyushu Univ.

MPSOC'03 17

Dynamic Reconfiguration of DRP

The connection among PEs and operations of PEs can be changed in every clock cycle.

By NEC

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SLIDE 18
  • H. Yasuura, Kyushu Univ.

MPSOC'03 18 External Memory

Data Cache

Instruction Cache DNA Buffer

RISC Core

Configuration memory DNA Matrix

BUS Controller

RISC Core

Configuration Memory

DNA Matrix

DNA Matrix

DAP/DNA - IP Flex (http://www.ipflex.com)

Traditional 32b embedded processor:DAP

32b ALU

  • r MUL
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  • H. Yasuura, Kyushu Univ.

MPSOC'03 19

DAP/DNA reconfigurable processor has the advanced features, including:

  • The DNA-Matrix architecture with dynamically

reconfigurable hardware.

  • Reconfiguration of the DNA-Matrix in one clock.
  • Parallel data processing, not sequential data

processing (Neumann Cycle), and extremely high performance with low power consumption due to the low clock frequency.

  • 1-2 digits higher performance compared to existing

solutions such as the CPUs and DSPs.

  • Dramatic reduction of the development cost and

period compared to ASIC and fully custom devices.

  • Hardware design with software method (C language)

enables flexible the design changes.

  • 600MTr. 225m2

Features of DAP/DNA

http://www.ipflex.com/english/product/dapdna_feature.html

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SLIDE 20
  • H. Yasuura, Kyushu Univ.

MPSOC'03 20

DNA(Distributed Network Architecture)

DNA (Distributed Network Architecture) Matrix Architecture The DNA-Matrix is a dataflow type accelerator arrayed 148 dynamic reconfigurable operation units. The wiring among elements can be changed dynamically and can quickly constitute parallel/pipeline processing system according to each application

  • peration unit processing. The DNA-

Matrix internal constituent information is stored in configuration memory, and its constitution changes in one clock depending on applications.

  • 148 of 32bit Operation Units
  • Data transfer between elements at

single cycle

  • Operating Frequency 100MHz

By IP Flex

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SLIDE 21
  • H. Yasuura, Kyushu Univ.

MPSOC'03 21

Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip

■ Background and Requirements ■ Platforms for Reconfigurable Computing

■ DRP ■ DAP/DNA

■ How to use Reconfigurable Computing in SoC

■ SysteMorph

■ Conclusion

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SLIDE 22
  • H. Yasuura, Kyushu Univ.

MPSOC'03 22

SysteMorph K. Murakami (SLRC, Kyushu Univ.)

n Silicon Sea-Belt Project n Just-in-Time (Dynamic, Online & Adaptive)

HW/ISA/SW Co-optimization Technology

n Applications:

n High Performance Computing

n Molecular Orbit Computation (Chemistry) n Reducing Cost and Energy

n Mobile Devices

n Mobile phones n Sensor networking n Reducing Energy and Increase Service Quality

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  • H. Yasuura, Kyushu Univ.

MPSOC'03 23

Design Issues in SysteMorph

n What to profile n How to profile them n How to discover hints for

  • ptimization

n What to optimize n How to optimize them n How to reconfigure HW/ISA/SW

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  • H. Yasuura, Kyushu Univ.

MPSOC'03 24

Functionality Morphing: An Example of SysteMorph

n Design issues in

SysteMorph

n What to profile n How to profile them n How to discover hints

for optimization

n What to optimize n How to optimize them n How to reconfigure

HW/ISA/SW

n Solutions in

functionality morphing

n Online hot-path profiling n Offload the functionality

  • f hot-paths from SW to

HW

n Online HW resynthesis n Reconfigurable co-

processor

n Dynamic binary

rewriting

By K. Murakami

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  • H. Yasuura, Kyushu Univ.

MPSOC'03 25

SysteMorph Software

Target Programs

SysteMorph Software

ISA Target Programs Instruction Execution

(5) Replace the hot path with a co- processor call (3) Transform the function of the hot path into a logic function

Application programs are running... Application programs are under

  • ptimization...

(2) Detect and predict hot program path

Functionality Morphing

  • Offload Hot Program Path to HW -

Processor Core

Reconfigurable Fabric

Profiler Processor Core

Reconfigurable Fabric

Profiler (4) Reconfigure the hardware of a reconfigurable co- processor (RCP)

SmartHardware Instruction Execution

(1) Monitor program path

By K. Murakami

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  • H. Yasuura, Kyushu Univ.

MPSOC'03 26

Offline Profiling

Summary of program behavior based on whole program trace Good for:

CO (Compiler Optimization) SRC (Static Reconfigurable Computing)

Online Profiling

Prediction based on current execution window of program Good for:

DCO (Dynamic CO) SysteMorph

Whole Whole Program Program Trace Trace Current Execution Window

Offline vs. Online Profiling

By K. Murakami

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SLIDE 27
  • H. Yasuura, Kyushu Univ.

MPSOC'03 27

Online Hot-Path Profiling

  • Algorithm -

n

Program Path

n

Existing Algorithms

n

Efficient path profiling

n

NET prediction

n

Our Algorithm

n

Profile the history of branch instruction’s behaviors (taken or not-taken, branch target)

n

If the execution frequency at a path head exceeds the threshold, select the path head (“A” in the figure) as a candidate of the hot path head

n

Traverse the object code, starting with the candidate (“A”), based on the branch history, and predict the hot path

By K. Murakami

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SLIDE 28
  • H. Yasuura, Kyushu Univ.

MPSOC'03 28 DAP DNA

Hot Path Profiler

Functionality Morphing Prototyping:

IP Flex DAP/DNA Powered by SysteMorph

SysteMorph Software

Target Programs

SysteMorph Software

ISA Target Programs Instruction Execution

Binary Rewriting Hardware Reconfiguration Adaptive HW/ISA/SW Co-optimization

DAP DNA

Hot Path Profiler

Hints for Optimization Hints for Optimization Online Profiling Online Profiling

Instruction Execution By K. Murakami

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SLIDE 29
  • H. Yasuura, Kyushu Univ.

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Offline vs. Online HW Synthesis

Offline HW Synthesis

HW configuration is synthesized prior to the program execution Good for:

SRC (Static Reconfigurable Computing)

Online HW Synthesis

HW configuration is synthesized in parallel with the program execution Good for:

SysteMorph

Algorithm C HDL SW HW Compilation HW Synthesis Program Execution Program Execution CDFG HW Synthesis HW

Time

HW Reconfiguration HW Reconfiguration

By K. Murakami

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SLIDE 30
  • H. Yasuura, Kyushu Univ.

MPSOC'03 30

Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip

■ Background and Requirements ■ Platforms for Reconfigurable Computing

■ DRP ■ DAP/DNA

■ How to use Reconfigurable Computing in SoC

■ SysteMorph

■ Conclusion

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SLIDE 31
  • H. Yasuura, Kyushu Univ.

MPSOC'03 31

Reconfigurable Computing

n

Several platforms are ready to use. System architectures and application techniques for SoC are key issues.

n

Cost Reduction

n

Reduce design, mask, and test costs.

n

Reuse an SoC device into different consumer products.

n

Customer Satisfaction

n

Optimize devices for multiple applications and varieties of usage.

n

Speed-up of Business

n

Introduce new services without change of devices.

n

Reliability and Security

n

Repairs and debugging on customer site.

n

Frequent update of security procedures.

n

Environment and Ecology

n

Reuse devices in revised services.

n

Minimization of energy consumption for each user.

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  • H. Yasuura, Kyushu Univ.

MPSOC'03 32

Korea Korea Kyushu Kyushu Okinawa Okinawa Taiwan Taiwan Hong Kong Hong Kong Singapore Singapore Shanghai Shanghai Fukuoka Fukuoka

Thank you for your attention.

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