Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip Hiroto Yasuura Kazuaki Murakami System LSI Research Center (SLRC) Kyushu University E-mail: yasuura@slrc.kyushu-u.ac.jp
Outline Outline ■ Background and Requirements ■ Platforms for Reconfigurable Computing ■ DRP ■ DAP/DNA ■ How to use Reconfigurable Computing in SoC ■ SysteMorph ■ Conclusion H. Yasuura, Kyushu Univ. MPSOC'03 2
Why Reconfigurable? Cost of Production n Drastic increase of design and mask cost is requesting new system n architectures, especially for small scale production less than 1M. Customer Satisfaction n Various kinds of customers, each of which has different requirement n and knowledge. A customized system for each user is attractive. Market Oriented SoC Design n The direction of the market changes quickly and various new services n are introduced. Reliability and Security n Repairs and debugging on customer site. n Changing system configuration for security. (cryptography etc.) n Global Environment Problem n Grow out of the throwaway society. n n Views of System Designers and Users H. Yasuura, Kyushu Univ. MPSOC'03 3
Example: Mobile Phone n New Services n I-mode (Internet Access: e-mail and WWW) n Built-in Digital Still Camera n Video Phone Service (MPEG-4 in NTT Foma) n Melody Calling n Music Down Load Service(MP3) n Electric Ticketing n Electric Money for Vending Machines n Simple Interface for Old People n Car Navigation Service n Needs for a new system architecture solution n Reconfigurable computing is a possible solution. H. Yasuura, Kyushu Univ. MPSOC'03 4
System Level Optimization n What n Parameters for optimization n Goals of optimization QoS (Function, Performance, Energy, Reliability, Security,…) n When n Design Stage, Compilation Stage, and Runtime n Who n Designers, Service Providers, and also Users n How n Reconfigurable Hardware Platforms n Software n Profiling and Design Optimization Techniques H. Yasuura, Kyushu Univ. MPSOC'03 5
Reconfigurable Computing When? Online Profiling & Reconfiguration EH SysteMorph SysteMorph DCO Runtime Runtime Offline Profiling & Reconfiguration SRC Compile Stage Compile Stage CO Design Stage Design Stage Codesign Offline Profiling & Optimization SW SW HW HW&SW HW HW&SW What? DCO: Dynamic Compilation/Optimization CO: Compiler Optimization EH: Evolvable Hardware By K. Murakami SRC: Static Reconfigurable Computing H. Yasuura, Kyushu Univ. MPSOC'03 6
Runtime Reconfiguration n Dynamic: Optimization is performed… n After SoC is shipped to the market n While SoC is used in the field n Online: Profiling and optimization are performed… n In parallel with the execution of application programs n During idle or sleeping time n Adaptive: Optimization is repeated… n In the form of a feedback loop H. Yasuura, Kyushu Univ. MPSOC'03 7
Analogy: Formula 1 The car is now The car is under After the running in reconfiguration reconfiguration, the course. the car returns to the course. Once the pit crew The pit crew is finds any hints monitoring the for behavior of reconfiguration, the car the car pits in By K. Murakami H. Yasuura, Kyushu Univ. MPSOC'03 8
When reconfiguration is done? Zzzzzz... A system is not always active. Reconfiguration can be done in idle and sleep time. H. Yasuura, Kyushu Univ. MPSOC'03 9
A Possible Business Model: OSP (Optimization Service Provider) Improve Profile OSP (Optimization your PDA your Users in the field while you favorites Service Provider) sleep Profiled Data Zzzzzz... Configuration Data Profile your habits Profile your Optimization behaviors Pit Center H. Yasuura, Kyushu Univ. MPSOC'03 10
Customizable Mobile Phone Your phone is evolving every battery charging! Optimization Service Provider Out-of-Suit Improving QoS in Sleep Optimization Sound quality On-line Profiling Battery life Key operation New services Debugging H. Yasuura, Kyushu Univ. MPSOC'03 11
Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip ■ Background and Requirements ■ Platforms for Reconfigurable Computing ■ DRP ■ DAP/DNA ■ How to use Reconfigurable Computing in SoC ■ SysteMorph ■ Conclusion H. Yasuura, Kyushu Univ. MPSOC'03 12
Platforms for Reconfigurable Computing ■ Dynamically Reconfigurable Processor: DRP by NEC ■ DAP/DNA by IP Flex ■ Dynamically Reconfigurable Circuits by Sony H. Yasuura, Kyushu Univ. MPSOC'03 13
Platforms for Reconfigurable Computing n Granularity of Reconfiguration n A Processor and Software n An Processor Array n Processing Elements n ALU, Multipliers, etc. n Logic Gates (FPGA) n Timing of Reconfiguration n Every Clock Cycle n Every Task Execution n Every Power-on H. Yasuura, Kyushu Univ. MPSOC'03 14
Dynamically Reconfigurable Processor:DRP 8KB 256B 8DRP cores on a Chip A DRP core includes 64 PEs. By NEC STC controls PEs. H. Yasuura, Kyushu Univ. MPSOC'03 15
PE of DRP • 16 instructions can be stored in the instruction memory of each PE. • An instruction specifies connections and operation of each processor. • The STC specifies the address of instruction . By NEC H. Yasuura, Kyushu Univ. MPSOC'03 16
Dynamic Reconfiguration of DRP The connection among PEs and operations of PEs can be changed in every clock cycle. By NEC H. Yasuura, Kyushu Univ. MPSOC'03 17
32b ALU DAP/DNA - IP Flex (http://www.ipflex.com) or MUL External Memory BUS Controller Instruction Cache DNA Buffer Data Cache Configuration Memory Configuration DNA memory DNA DNA Matrix Matrix Matrix RISC RISC Core Core Traditional 32b embedded processor:DAP H. Yasuura, Kyushu Univ. MPSOC'03 18
Features of DAP/DNA DAP/DNA reconfigurable processor has the advanced features, including: • The DNA-Matrix architecture with dynamically reconfigurable hardware. • Reconfiguration of the DNA-Matrix in one clock. • Parallel data processing, not sequential data processing (Neumann Cycle), and extremely high performance with low power consumption due to the low clock frequency. • 1-2 digits higher performance compared to existing solutions such as the CPUs and DSPs. • Dramatic reduction of the development cost and period compared to ASIC and fully custom devices. • Hardware design with software method (C language) enables flexible the design changes. 600MTr. 225m 2 http://www.ipflex.com/english/product/dapdna_feature.html H. Yasuura, Kyushu Univ. MPSOC'03 19
DNA(Distributed Network Architecture) DNA (Distributed Network Architecture) Matrix Architecture The DNA-Matrix is a dataflow type accelerator arrayed 148 dynamic reconfigurable operation units. The wiring among elements can be changed dynamically and can quickly constitute parallel/pipeline processing system according to each application operation unit processing. The DNA- Matrix internal constituent information is stored in configuration memory, and its constitution changes in one clock depending on applications. • 148 of 32bit Operation Units • Data transfer between elements at single cycle By IP Flex • Operating Frequency 100MHz H. Yasuura, Kyushu Univ. MPSOC'03 20
Reconfigurable Computing Reconfigurable Computing for System on a Chip for System on a Chip ■ Background and Requirements ■ Platforms for Reconfigurable Computing ■ DRP ■ DAP/DNA ■ How to use Reconfigurable Computing in SoC ■ SysteMorph ■ Conclusion H. Yasuura, Kyushu Univ. MPSOC'03 21
SysteMorph K. Murakami (SLRC, Kyushu Univ.) n Silicon Sea-Belt Project n Just-in-Time (Dynamic, Online & Adaptive) HW/ISA/SW Co-optimization Technology n Applications: n High Performance Computing n Molecular Orbit Computation (Chemistry) n Reducing Cost and Energy n Mobile Devices n Mobile phones n Sensor networking n Reducing Energy and Increase Service Quality H. Yasuura, Kyushu Univ. MPSOC'03 22
Design Issues in SysteMorph n What to profile n How to profile them n How to discover hints for optimization n What to optimize n How to optimize them n How to reconfigure HW/ISA/SW H. Yasuura, Kyushu Univ. MPSOC'03 23
Functionality Morphing: An Example of SysteMorph n Design issues in n Solutions in SysteMorph functionality morphing n Online hot-path profiling n What to profile n Offload the functionality n How to profile them of hot-paths from SW to n How to discover hints HW for optimization n Online HW resynthesis n What to optimize n Reconfigurable co- n How to optimize them processor n How to reconfigure n Dynamic binary HW/ISA/SW rewriting By K. Murakami H. Yasuura, Kyushu Univ. MPSOC'03 24
Functionality Morphing - Offload Hot Program Path to HW - Application programs are under Application programs are running... optimization... (3) Transform the (1) Monitor function of the (2) Detect and program path hot path into a predict hot (5) Replace the hot logic function program path path with a co- processor call Target Target SysteMorph SysteMorph Programs Programs Software Software Instruction ISA Instruction Execution Execution Profiler Profiler Processor Processor Core Core Reconfigurable Reconfigurable Fabric Fabric SmartHardware (4) Reconfigure the hardware of a reconfigurable co- By K. Murakami processor (RCP) H. Yasuura, Kyushu Univ. MPSOC'03 25
Recommend
More recommend
