A Framework for Automatic Generation A Framework for Automatic Generation of Configuration Files for a Custom of Configuration Files for a Custom Hardware/Software RTOS Hardware/Software RTOS Jaehwan Lee* Lee* Jaehwan Kyeong Keol Keol Ryu Ryu* * Kyeong Vincent J. Mooney III + + Vincent J. Mooney III {jaehwan jaehwan, , kkryu kkryu, , mooney}@ece.gatech.edu mooney}@ece.gatech.edu { http://codesign.ece.gatech.edu codesign.ece.gatech.edu http:// + Assistant Professor, *School of Electrical and Computer Engineer + Assistant Professor, *School of Electrical and Computer Engineering ing + Adjunct Assistant Professor, College of Computing + Adjunct Assistant Professor, College of Computing Georgia Institute of Technology Georgia Institute of Technology 26 June 2002 at ERSA HW/SW RTOS Project of the HW/SW Codesign Codesign Group at GT Group at GT 26 June 2002 at ERSA HW/SW RTOS Project of the HW/SW
Outline Outline � Introduction � Goals � Motivation � Methodology � Experimental Results � Conclusion June 2002 at ERSA 2 HW/SW RTOS Project June 2002 at ERSA 2 HW/SW RTOS Project
Introduction Introduction � Specify custom HW/SW RTOS in a graphical user interface (GUI) Software RTOS library � Generate configuration files Makefile used to make a custom RTOS User GUI tool • A custom RTOS may contain HW User.h input (as well as SW) components Verilog � Compile both hardware and File(s) Hardware Base software with an application RTOS Architecture library library � Simulate the system to evaluate the result June 2002 at ERSA 3 HW/SW RTOS Project June 2002 at ERSA 3 HW/SW RTOS Project
Goals Goals � To help the user examine which configuration is most suitable for the user’s specific applications � To help the user explore the RTOS design space after chip fabrication as well as before chip fabrication � To help the user examine different system-on-a- chip (SoC) architectures subject to a custom RTOS June 2002 at ERSA 4 HW/SW RTOS Project June 2002 at ERSA 4 HW/SW RTOS Project
Motivation (1/5) Motivation (1/5) � HW/SW RTOS partitioning approach � Three previous innovations in HW/SW RTOS components • SoCLC: System-on-a-Chip Lock Cache • SoCDMMU: System-on-a-Chip Dynamic Memory Management Unit • SoCDDU: System-on-a-Chip Deadlock Detection Unit June 2002 at ERSA 5 HW/SW RTOS Project June 2002 at ERSA 5 HW/SW RTOS Project
Motivation (2/5) Motivation (2/5) � System-on-a-Chip Lock Cache • A hardware mechanism that resolves the critical section (CS) interactions among PEs • Lock variables are moved into a separate “lock cache” outside of the memory • Improving the performance criteria in terms of lock latency, lock delay and bandwidth consumption June 2002 at ERSA 6 HW/SW RTOS Project June 2002 at ERSA 6 HW/SW RTOS Project
Motivation (3/5) Motivation (3/5) � SoCDMMU: System-on-a-Chip Dynamic Memory Management Unit • Provides fast, deterministic and yet dynamic memory management of a global on-chip memory • Achieves flexible, efficient memory utilization • Provides APIs for applications June 2002 at ERSA 7 HW/SW RTOS Project June 2002 at ERSA 7 HW/SW RTOS Project
Motivation (4/5) Motivation (4/5) � SoCDDU: System-on-a-Chip Deadlock Detection Unit • Performs a novel parallel hardware deadlock detection based on implementing deadlock searches on the resource allocation matrix in hardware • Provides a very fast deadlock detection at run-time with dedicated hardware performing simple bit-wise boolean operations • Reduces deadlock detection time by 99% as compared to software • Requires at most O(2*min(m,n)) iterations as opposed to O(m*n) required by all previously reported (sequential) software algorithms June 2002 at ERSA 8 HW/SW RTOS Project June 2002 at ERSA 8 HW/SW RTOS Project
Motivation (5/5) Motivation (5/5) Constraints about using three previous innovations • Perhaps not enough chip space for all three of them • All of them may not be necessary ⇒ Our framework • Enables automatic generation of different mixes of the three previous innovations for different versions of a HW/SW RTOS • Can be generalized to instantiate additional HW or SW RTOS components June 2002 at ERSA 9 HW/SW RTOS Project June 2002 at ERSA 9 HW/SW RTOS Project
Methodology (1/2) Methodology (1/2) � Translates the user choices into a custom RTOS • Given the IP library of processors Software RTOS and HW/SW RTOS components library Makefile � Generates configuration files to glue together a custom RTOS User GUI tool User.h input executable in the Seamless Co- Verification Environment from Verilog Mentor Graphics File Hardware Base RTOS Architecture • Makefile and User.h for SW link library library • Verilog header file for HW glue June 2002 at ERSA 10 HW/SW RTOS Project June 2002 at ERSA 10 HW/SW RTOS Project
Methodology (2/2) Methodology (2/2) � Explores the HW/SW RTOS design space defined by the available HW/SW RTOS components easily Application SW Software Compile RTOS library and Makefile HW/SW Link Co- Result Simulation and GUI tool User Feedback User.h input HW Verilog Compile File Hardware Base RTOS Architecture library library June 2002 at ERSA 11 HW/SW RTOS Project June 2002 at ERSA 11 HW/SW RTOS Project
Our RTOS and Possible Target SoC SoC Our RTOS and Possible Target H/W S/W RTOS � A multiprocessor System-on-a-Chip ( Base architecture) � A multiprocessor RTOS � Application(s) running on the SoC using the RTOS APIs June 2002 at ERSA 12 HW/SW RTOS Project June 2002 at ERSA 12 HW/SW RTOS Project
Our RTOS in Detail Our RTOS in Detail � Atalanta software RTOS • A multiprocessor SoC RTOS � The RTOS and device drivers are loaded into the L2 cache memory H/W • All Processing Elements (PEs) S/W RTOS � share the kernel code and data structures � Hardware RTOS components are downloaded into the reconfigurable logic June 2002 at ERSA 13 HW/SW RTOS Project June 2002 at ERSA 13 HW/SW RTOS Project
Selectable RTOS IP components Selectable RTOS IP components � Software (Atalanta RTOS) • Inter-Process Communication (IPC) components (semaphore, queue, event, mailbox, etc) • CPU schedulers (priority, round-robin) • Memory management module (gmm) • Deadlock detection module (ddm) � Hardware • SoC Lock Cache for fast IPC (SoCLC) • Dynamic Memory Management Unit (SoCDMMU) • Deadlock Detection Unit (SoCDDU) June 2002 at ERSA 14 HW/SW RTOS Project June 2002 at ERSA 14 HW/SW RTOS Project
Implementation (1/8) Implementation (1/8) SW may over- ride task size SW module IPC module linking method linking method HW integration method June 2002 at ERSA 15 HW/SW RTOS Project June 2002 at ERSA 15 HW/SW RTOS Project
Implementation (2/8) Implementation (2/8) with Example Use of GUI Tool � The user • Selects � Deadlock detection SW module � Semaphores for synchronization � SoCLC for critical section • Clicks Generate button � The tool • Generates � Makefile & User.h � Verilog header file June 2002 at ERSA 16 HW/SW RTOS Project June 2002 at ERSA 16 HW/SW RTOS Project
Implementation (3/8) Implementation (3/8) 1) Software module linking method • Command-line object inclusion method (well-known) • Used for the same function but different implementations • Implemented in Makefile • Used for linking the deadlock detection SW module in the example June 2002 at ERSA 17 HW/SW RTOS Project June 2002 at ERSA 17 HW/SW RTOS Project
Implementation (4/8) Implementation (4/8) 1) Software module linking method (cont’d) $(LD) – o $@ $(OTHER_OBJS) $(OPT_OBJ1) $(OPT_OBJ2) $(LIBRARY) Making to Stage gcc – o ddutest.x [all other objects including ddutest.o] ddm.o atalanta.a Makefile GUI OTHER_OBJS = ddutest.o … Tool OPT_OBJ1 = ddm.o OPT_OBJ2 = (blank) Software component selection ddutest.x ddm.o Linking X gmm.o Stage June 2002 at ERSA 18 HW/SW RTOS Project June 2002 at ERSA 18 HW/SW RTOS Project
Implementation (5/8) Implementation (5/8) 2) Inter-process communication module linking method • Library function linking method (common) • Implemented in User.h • Used for the semaphore function in the example June 2002 at ERSA 19 HW/SW RTOS Project June 2002 at ERSA 19 HW/SW RTOS Project
Implementation (6/8) Implementation (6/8) 2) IPC module linking method (cont’d) GUI Generated Configuration Tool #define semaphores TRUE user.h included application Library (Atalanta.a) ddutest.x user.c user.i user.o Semaphore functions Pre-processing Queue functions Making Mailbox functions Linking Stage Stage Event functions ddutest.c ddutest.o Other functions Selection flow of IPC methods … June 2002 at ERSA 20 HW/SW RTOS Project June 2002 at ERSA 20 HW/SW RTOS Project
Implementation (7/8) Implementation (7/8) 3) HW RTOS component integration method MPC750-1 MPC750-2 MPC750-3 MPC750-4 � Novel HW integration method � Construct a Verilog header file L1 L1 L1 L1 � Integrate user-selected HW RTOS components into the Base architecture SoCLC Arbiter, Memory � Start with an SoCLC architecture Intr. controller description (an example with SoCLC) Reconfig. controller, and Logic Clock memory June 2002 at ERSA 21 HW/SW RTOS Project June 2002 at ERSA 21 HW/SW RTOS Project
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