[PPT] - 30 nm I n 0.7 Ga 0.3 As I nverted-type HEMT with Reduced Gate PowerPoint Presentation

SLIDE 1

30 nm I n0.7Ga0.3As I nverted-type HEMT with Reduced Gate Leakage Current g for Logic Applications

T.-W. Kim, D.-H. Kim* and J. A. del Alamo

Microsystems Technology Laboratories MIT Presently with Teledyne Scientific Sponsors: Intel & FCRP-MSD Fabrication: MTL, NSL, SEBL Ackno ledgements MBE Technolog for epi afer IEDM

December 7-9, 2009

1

Acknowledgements:MBE Technology for epi wafer UNIST in Korea for TEM analysis

SLIDE 2

Outline

1. Introduction
2. Device Technology
3. Logic Characteristics
4. Benchmarking with normal HEMT and

Si CMOS Si CMOS 5 Conclusions

2

5. Conclusions

SLIDE 3

I nsulator Scaling in I I I -V HEMTs

M ti ti

f f

Motivation : - III-V HEMT: Model system for future III-V logic FETs

HEMT scaling: Lg   tins 

 

Problem: tins   IG 

10

4

10

3

tins = 10 nm tins = 7 nm 10

6

10

5

m]

tins = 4 nm

InAlAs/InGaAs HEMT Lg = 30 nm

ID I

tins = 4 nm

10

8

10

7

ID, IG [A/

Lg 30 nm

IG

7 nm

<del Alamo, TWHM 09>

1.00
0.75
0.50
0.25

0.00 0.25 0.50 10

10

10

9

VDS = 0.5 V

10 nm

3

VGS [V]

Inverted HEMT design: reduced IG

SLIDE 4

Concept of I nverted HEMT

<Normal HEMT > <Inverted HEMT > <Normal HEMT > <Inverted HEMT > Insulator Cap.

Gate

Insulator Cap. Channel Barrier Channel Barrier Si  doping

0 4 0.6

E Inverted HEMT VGS = +0.25 V

2.5 3.0 0 4 0.6

Normal HEMT VGS = +0.3 V

2.5 3.0 0.0 0.2 0.4

Electron density [ Profiles [eV]

1.5 2.0 0 0 0.2 0.4

Electron density Profiles [eV]

1.5 2.0 2.5 10 20 30 40 50

0.4
0.2

0.0

[x 10

18/cm 3]

CB P

ns,ch = 1.5 X 1012/cm2

0.0 0.5 1.0

0.4
0.2

0.0

ns,ch = 1.6 X 1012/cm2

y [x 10

18/cm 3]

CB P

0.0 0.5 1.0

4

Lower leakage current due to higher barrier under gate

10 20 30 40 50

Vertical depth [nm]

10 20 30 40 50

Vertical depth [nm]

SLIDE 5

Trade-off of I nverted HEMT

 : Access region  : Contact region

0.8 4

 

0.8 4 0 2 0.4 0.6

Electron De iles [eV]

2 3 0 2 0.4 0.6

Electron Den ile [eV]

2 3

0.2

0.0 0.2

ensity [10

18/cm 3]

CB Profi

ns,ch = 0 6X1012/ 2

1 2

0.2

0.0 0.2

nsity [10

18/cm 3]

CB Prof

1 2

ns,ch = 0 68 x 1012 /cm2

20 40 60 80 100

0.4

Vertical depth [nm]

0.6X1012/cm2

10 20 30 40 50 60 70

0.4

Vertical depth [nm]

0.68 x 10 /cm

ns,ch ~ 2.7 x 1012/cm2 for Normal HEMT ns,ch ~ 3 x 1012/cm2 for Normal HEMT

5

Problem: - low ns in access region
large energy barrier under contact region

SLIDE 6

New Approach

Gate

New  doping layer

0.6 4

 

 : Access region  : Contact region

0.6 4 0.2 0.4

Electron Dens

files [eV]

2 3 0.2 0.4 Electron Dens

file [eV]

2 3

0.2

0.0

sity [10

18/cm 3]

CB Pro

ns,ch = 2.7X1012/cm2

1

0.2

0.0 sity [10

18/cm 3]

CB Pro 1

ns,ch = 2 4 x 1012 /cm2

20 40 60 80

0.4

Vertical depth [nm]

2.7X10 /cm

ns,ch ~ 2.7 x 1012/cm2 for Normal HEMT ns,ch ~ 3 x 1012/cm2 for Normal HEMT

10 20 30 40 50 60

0.4

Vertical depth [nm]

2.4 x 1012 /cm2

6

High ns in access region
Low barrier in contact region

SLIDE 7

Epitaxial Heterostructure

n+ In0.65Ga0.35As 5 nm n+ In0.53Ga0.47As 15 nm

Cap

0.53 0.47

n+ In0.52Al0.48As 15 nm InP 6 nm

Si -doping Etch stopper

In0.52Al0.48As 2 nm In0.52Al0.48As 8 nm In Ga As 2 nm

S  dop g Barrier

In0.53Ga0.47As 2 nm In0.7Ga0.3As 8 nm In0.53Ga0.47As 3 nm

Channel

In0.52Al0.48As 5 nm In0.52Al0.48As

Back Barrier + Buffer

n,Hall = 9,800 cm2/V-sec

7

S. I. InP

Substrate

SLIDE 8

Device Technology

S

Cap

D

Oxide

Lside

Cap

Lg

Etch stopper Barrier

tins Lside

Channel Buffer

ins

tch

Triple-recess process
tins = 4 nm, Lside = 80 nm
Gate: Ti/Pt/Au

8 Buffer

Lg: 30 - 130 nm

SLIDE 9

Output & Transfer Char. : LG = 30 nm

0.8

V =0 3 V

0.5 0.6 1200 1400

VDS=0.5 V

0.4 0.6

0.1 0.2 VGS=0.3 V

mA/m]

0.3 0.4

GM [mS mA/m]

800 1000 1200 0.2

0.1

ID [m

0.1 0.2

S/mm] ID [m

200 400 600 0.0 0.2 0.4 0.6 0.8 1.0 0.0

0.2

VDS [V]

0.4
0.2

0.0 0.2 0.4 0.0

VGS [V]

00

Good ID saturation, pinch-off behavior G 1 27 S/ @ V 0 5 V

9

Gm = 1.27 S/mm @ VDS=0.5 V

SLIDE 10

3

Subthreshold Char. : Lg = 30 nm

10

4

10

3

ID

10

6

10

5

VDS= 0.5 V VDS= 0.05 V [A/m]

10

8

10

7

IG ID & IG [

0 6
0 4
0 2

0 0 0 2 0 4 10

10

10

9
0.6
0.4
0.2

0.0 0.2 0.4

VGS [V]

DIBL = 118 mV/V, S = 83 mV/dec.

10

Excellent IOFF

 ION/IOFF= 3.9 X 104 for VDS = 0.5 V

SLIDE 11

fT & fmax Char. : Lg = 30 nm

40 30

U

]

H21 20 MAG/MSG fmax= 550 GHz

Gain [dB]

10 fT= 500 GHz VGS=0.2 V VDS=0.8 V 10

9

10

11

10

12

Frequency [Hz]

VDS 0.8 V

11

fT=500 GHz & fmax=550 GHz Highest fT & fmax reported on Inverted HEMTs

SLIDE 12

I nverted vs. Normal HEMTs: I G

4

10

3

VDS = 50 mV Inverted HEMT Normal HEMT VDS = 0.5 V

ID

6

10

5

10

4

VDS = 50 mV VDS = 0.5 V

DS

m]

Lg = 30 nm 10

7

10

6

VDS = 50 mV VDS = 0.5 V

& IG [A/m

IG 10

9

10

8

ID

IG

<D -H KIM IPRM 09>

0.50
0.25

0.00 0.25 10

10

VGS [V]

12

Inverted HEMT:  ~100 X less IG than normal HEMT

<D.-H. KIM IPRM 09>

SLIDE 13

I nverted vs. Normal HEMTs: I ON/ I OFF vs. Lg

10

3

10

2

Inverted HEMT Normal HEMT

ION

6

10

7 6

10

5

10

4

I A/m] 10

5

10

6

10

8

10

7

10

6

ION/IOFF ION & IOFF [A

3

10

4

20 40 60 80 100 120 140 10

10

10

9

IOFF 10

2

10

3

VDS = 0.5 V

Inverted HEMT:

Lg [nm]

13

 Excellent ION/IOFF scalability down to Lg = 30 nm

SLIDE 14

I nverted vs. Normal HEMTs: gmi

3.2 Inverted HEMT : n,Hall = 9,800 cm

2/V-s

Normal HEMT n,Hall = 11,000 cm

2/V-s

g from S parameters

2 4 2.8 m]

gmi from S-parameters

2.0 2.4

g t

& gm,ext [S/mm

gmi

1.2 1.6

gm,ext

gmi & VDS=0 5V

Inverted HEMTs:

10 100 Gate Length [nm] VDS=0.5V

Inverted HEMTs:

Lower values of gmi: from reduced  and velocity
Better gmi scalability down to 30 nm

14

SLIDE 15

I nverted vs. Normal HEMTs: Rs

<Using gate current injection technique>

0.40

Inverted HEMT

0 32 0.36

Inverted HEMT Normal HEMT ]

RS=0.27 ohm.mm Rsh =100 ohm/sq 0.28 0.32

Rs

* [ohm.mm]

0 20 0.24 Rsh =70 ohm/sq RS=0.225 ohm.mm

R

40 80 120 160 0.20 RS 0.225 ohm.mm

Lg [nm] 15

Higher Rs in inverted HEMT Why?  Lower ns in access region, higher Rc

SLIDE 16

I nverted vs. Normal HEMTs: fT and fmax

600 700

Inverted HEMT Normal HEMT

0.30 Inverted HEMT 400 500 600

fmax fT

GHz]

fT

0.20 0.25 ce go [S/mm] Normal HEMT 200 300

fmax

fT & fmax [G

0.10 0.15 ut conductanc

0.3
0.2
0.1

0.0 0.1 0.2 0.3 0.4 0.5 100

V [V]

Lg = 30 nm

VDS = 0.8 V

VDS = 0.8 V Lg = 30 nm

0.3
0.2
0.1

0.0 0.1 0.2 0.3 0.4 0.00 0.05 Outpu V [V]

Inverted HEMTs:  Lower f & higher f

VGS [V]

16

 Lower fT & higher fmax  Improved go: possibly due to lower ns in access region

SLIDE 17

Benchmarking : SS & DI BL

180

]

I t d HEMT

Si FETs (IEDM) 400

Inverted HEMT

Si FETs (IEDM)

140 160

pe [mV/dec]

Inverted HEMT Normal HEMT

200 300

V/V]

Normal HEMT 100 120

hreshold Slo

100 200

DIBL [mV

10 100 60 80

Gate Length [nm] Subth

10 100

Gate Length [nm]

Excellent SCE of inverted HEMT

Gate Length [nm] Gate Length [nm] 17 17

SLIDE 18

Benchmarking : I ON vs. I Leak

0.5

VDD = 0.5 V x 10

3

InGaAs normal HEMT Lg = 30 nm

) ( 2 1

,ON G OFF leak

I I I  

0.4

g

InGaAs Inverted HEMT Lg = 30 nm 65 nm HP-CMOS (Lg = 35 nm)

0 2 0.3

N [A/m]

65 nm LP-CMOS (Lg = 55nm)

0.1 0.2

ION

10

9

10

8

10

7

10

6

0.0

18

 At Ileak = 100 nA/μm, 1.3X higher ION than 65 nm HP CMOS

Ileak [A/m]

SLIDE 19

Benchmarking : CV/ I vs. Lg

10

Inverted HEMTs Normal HEMTs

1 I G A HEMT

AY [psec]

1 In0.7Ga0.3As HEMTs (VDD = 0.5V)

GATE DELA

10 10

1

10

2

10

3

0.1

G

Si NMOSFETs (VDD = 1.1~1.3V)

Gate Length, Lg [nm]

Inverted HEMT:

19

 Comparable Gate delay with Lg but at lower VDD

< Ref. : Chau et al. (T-Nano 2005) >

SLIDE 20

Conclusions

Inverted InGaAs HEMT

S li b fit – Scaling benefit:

Reduced Ig allows for further Lg scaling

At 30 i t d HEMT hibit ll t h t i ti – At 30 nm, inverted HEMTs exhibit excellent characteristics:

DIBL < 120 mV/V, S < 85 mV/dec and ION/IOFF ~ 4 x 104
f > 500 GHz and f

> 550 GHz CV/I ~ 1 psec

fT > 500 GHz and fmax > 550 GHz, CV/I ~ 1 psec
Inverted InGaAs HEMT: promising layer structure for future

Inverted InGaAs HEMT: promising layer structure for future high-K/III-V MOSFET

20 20