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MC602 – 2011
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MC 602
IC/Unicamp 2011s2 Prof Mario Côrtes
MC602 – 2011
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Tópicos
- Máquinas de estados
– Moore – Mealy
- Dois templates para implementação em VHDL
VHDL Mquina de Estados (FSM) 1 MC602 2011 Tpicos IC-UNICAMP - - PowerPoint PPT Presentation
VHDL Mquina de Estados (FSM) 1 MC602 2011 Tpicos IC-UNICAMP - - PowerPoint PPT Presentation
MC 602 IC-UNICAMP IC/Unicamp 2011s2 Prof Mario Crtes VHDL Mquina de Estados (FSM) 1 MC602 2011 Tpicos IC-UNICAMP Mquinas de estados Moore Mealy Dois templates para implementao em VHDL 2 MC602 2011
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Combinational circuit Flip-flops Clock Q W Z Combinational circuit
Forma geral de um circuito síncrono
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Máquina de Moore
C z 1 =
⁄ ⁄ ⁄ ⁄
Reset B z =
⁄ ⁄ ⁄ ⁄
A z =
⁄ ⁄ ⁄ ⁄
w = w 1 = w 1 = w = w = w 1 =
Clockcycle: t t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
w : 1 1 1 1 1 1 1 z : 1 1 1
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Present Next state Output state
w = 0 w = 1 z
A A B B A C C A C 1
C z 1 = ⁄ ⁄⁄ ⁄ Rese t B z 0 = ⁄ ⁄⁄ ⁄ A z 0 = ⁄ ⁄⁄ ⁄ w = w 1 = w 1 = w = w = w 1 =
Diagrama de Estados
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Implementação
Combinational circuit Combinational circuit Clock y2 z w y1 Y
1
Y
2
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Atribuição de Estado
Present Next state state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 00 00 01 B 01 00 10 C 10 00 10 1 11 dd dd d
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IC-UNICAMP w 00 01 11 10 1 1 y 2 y 1 Y 1 wy 1 y 2 = w 00 01 11 10 1 d 1 d y 2 y 1 Y 2 wy 1 y 2 wy 1 y 2 + = d d 1 1 1 d y 1 z y 1 y 2 = 1 y 2 Y 1 wy 1 y 2 = Y 2 wy 1 wy 2 + = z y 2 = w y 1 y 2 + ( ) = Ignoring don't cares Using don't cares
Derivação das expressões lógicas
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D Q Q D Q Q Y
2
Y
1
w Clock z y
1
y
2
Resetn
Circuito sequencial
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t t
1
t
2
t
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t
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t
5
t
6
t
7
t
8
t
9
t
10
1 1 1 1 Clock w y
1
y
2
1 z
Timing diagram
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FSM de Moore
USE ieee.std_logic_1164.all; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END simple; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C); -- Tipo Enumerado para
- - definir os Estados
SIGNAL y : State_type; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN -- A é o estado inicial y <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN con’t ...
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FSM de Moore
CASE y IS WHEN A => IF w = '0’ THEN y <= A; ELSE y <= B; END IF; WHEN B => IF w = '0’ THEN y <= A; ELSE y <= C; END IF; WHEN C => IF w = '0' THEN y <= A; ELSE y <= C; END IF; END CASE; END IF; END PROCESS; z <= '1' WHEN y = C ELSE '0'; END Behavior;
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FSM de Moore - Simulação
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FSM de Moore - Simulação
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FSM de Moore Codificação Alternativa (2 processos)
USE ieee.std_logic_1164.all; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END simple; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C); SIGNAL y_present, y_next : State_type;
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FSM de Moore Codificação Alternativa (2 processos)
BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A; ELSE y_next <= B; END IF; WHEN B => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF;
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FSM de Moore - Codificação Alternativa
WHEN C => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; END CASE; END PROCESS; PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN y_present <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next; END IF; END PROCESS; z <= '1' WHEN y_present = C ELSE '0'; END Behavior;
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FSM - Especificando a Atribuição de Estados
ARCHITECTURE Behavior OF simple IS TYPE State_TYPE IS (A, B, C); ATTRIBUTE ENUM_ENCODING : STRING; ATTRIBUTE ENUM_ENCODING OF State_type: TYPE IS "00 01 11"; SIGNAL y_present, y_next : State_type; BEGIN con’t ...
- Obs: Atributo Enum_Encoding é específico da ferramenta Quartus. Esta
solução pode não funcionar em outras ferramentas CAD
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LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY simple IS PORT ( Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END simple; ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A; ELSE y_next <= B; END IF;
… con’t
FSM - Especificando a Atribuição de Estados
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WHEN B => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; WHEN C => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; WHEN OTHERS => y_next <= A; END CASE; END PROCESS; PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN y_present <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next; END IF; END PROCESS; z <= '1' WHEN y_present = C ELSE '0'; END Behavior;
FSM - Especificando a Atribuição de Estados
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A w = z = ⁄ ⁄ ⁄ ⁄ w 1 = z 1 = ⁄ ⁄ ⁄ ⁄ B w = z = ⁄ ⁄ ⁄ ⁄ Reset w 1 = z = ⁄ ⁄ ⁄ ⁄
Máquina de Mealy
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FSM de Mealy
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mealy IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END mealy; … con’t
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FSM de Mealy
ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B); SIGNAL y : State_type; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A; ELSE y <= B; END IF; WHEN B => IF w = '0' THEN y <= A; ELSE y <= B; END IF; END CASE; END IF; END PROCESS; … con’t
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FSM de Mealy
PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0'; WHEN B => z <= w; END CASE; END PROCESS; END Behavior;