Verilog HDL:Digital Design and Modeling Chapter 6 User-Defined - - PDF document

Chapter 6 User-Defined Primitives 1

Verilog HDL:Digital Design and Modeling Chapter 6 User-Defined Primitives

Chapter 6 User-Defined Primitives 2

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//3-input AND gate as a udp primitive udp_and3 (z1, x1, x2, x3);//output is listed first input x1, x2, x3;

• utput z1;

//state table table //inputs are in the same order as the input list // x1 x2 x3 : z1; comment is for readability : 0; 1 : 0; 1 : 0; 1 1 : 0; 1 : 0; 1 1 : 0; 1 1 : 0; 1 1 1 : 1; endtable endprimitive

Figure 6.1 A UDP for a 3-input AND gate. Page 231

//UDP for a 2-input AND gate primitive udp_and2 (z1, x1, x2); //output is listed first input x1, x2;

• utput z1;

//define state table table //inputs are the same order as the input list // x1 x2 : z1; comment is for readability : 0; 1 : 0; 1 : 0; 1 1 : 1; endtable endprimitive

Figure 6.5 UDP for a 2-input AND gate.

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//UDP for a 3-input OR gate primitive udp_or3 (z1, x1, x2, x3); //output is listed first input x1, x2, x3;

• utput z1;

//define state table table //inputs are the same order as the input list // x1 x2 x3 : z1; comment is for readability : 0; 1 : 1; 1 : 1; 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 1; endtable endprimitive

Figure 6.6 UDP for a 3-input OR gate. Page 232

//sum of products using udps for the AND gate and OR gate module udp_sop (x1, x2, x3, x4, z1); input x1, x2, x3, x4;

• utput z1;

//define internal nets wire net1, net2, net3; //instantiate the udps udp_and2 inst1 (net1, x1, x2); udp_and2 inst2 (net2, x3, x4); udp_and2 inst3 (net3, ~x2, ~x3); udp_or3 inst4 (z1, net1, net2, net3); endmodule

Figure 6.7 Module for the sum-of-products logic of Figure 6.2 using UDPs.

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//test bench for sum of products using udps module udp_sop_tb; reg x1, x2, x3, x4; wire z1; //apply input vectors initial begin: apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {x1, x2, x3, x4} = invect [4:0]; #10 $display ("x1x2x3x4 = %b, z1 = %b", {x1, x2, x3, x4}, z1); end end //instantiate the module into the test bench udp_sop inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .z1(z1) ); endmodule

Figure 6.8 Test bench for the sum-of-products module of Figure 6.7.

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x1x2x3x4 = 0000, z1 = 1 x1x2x3x4 = 0001, z1 = 1 x1x2x3x4 = 0010, z1 = 0 x1x2x3x4 = 0011, z1 = 1 x1x2x3x4 = 0100, z1 = 0 x1x2x3x4 = 0101, z1 = 0 x1x2x3x4 = 0110, z1 = 0 x1x2x3x4 = 0111, z1 = 1 x1x2x3x4 = 1000, z1 = 1 x1x2x3x4 = 1001, z1 = 1 x1x2x3x4 = 1010, z1 = 0 x1x2x3x4 = 1011, z1 = 1 x1x2x3x4 = 1100, z1 = 1 x1x2x3x4 = 1101, z1 = 1 x1x2x3x4 = 1110, z1 = 1 x1x2x3x4 = 1111, z1 = 1

Figure 6.9 Outputs for the test bench of Figure 6.8 for the sum-of-products module

• f Figure 6.7.

Figure 6.10 Waveforms for the test bench of Figure 6.8 for the sum-of-products module of Figure 6.7.

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//UDP for a 2-input NAND gate primitive udp_nand2 (z1, x1, x2); input x1, x2;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 : z1; comment is for readability : 1; 1 : 1; 1 : 1; 1 1 : 0; endtable endprimitive

Figure 6.14 UDP for a 2-input NAND gate.

//UDP for a 3-input NAND gate primitive udp_nand3 (z1, x1, x2, x3); input x1, x2, x3;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 x3 : z1; comment is for readability : 1; 1 : 1; 1 : 1; 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 0; endtable endprimitive

Figure 6.15 UDP for a 3-input NAND gate.

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//UDP for a 4-input NAND gate primitive udp_nand4 (z1, x1, x2, x3, x4); input x1, x2, x3, x4;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 x3 x4 : z1; comment is for readability : 1; 1 : 1; 1 : 1; 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 1; 1 1 : 1; 1 1 1 : 1; 1 1 1 : 1; 1 1 1 1 : 0; endtable endprimitive

Figure 6.16 UDP for a 4-input NAND gate.

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//UDPs to design logic to activate segment a of an LED module udp_seg_a (x1, x2, x3, x4, z1); input x1, x2, x3, x4;

• utput z1;

//define internal nets wire net1, net2, net3, net4; udp_nand3 (net2, ~x1, x2, x4); udp_nand3 (net3, x1, ~x2, ~x3); udp_nand3 (net4, ~x2, ~x3, ~x4); udp_nand4 (z1, net1, net2, net3, net4); endmodule

Figure 6.17 Module with UDPs to activate segment a of a 7-segment LED.

//test bench for udp_seg_a module udp_seg_a_tb; reg x1, x2, x3, x4; wire z1; initial //apply input vectors begin: apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {x1, x2, x3, x4} = invect [4:0]; #10 $display ("x1x2x3x4 = %b, z1 = %b", {x1, x2, x3, x4}, z1); end end //instantiate the module into the test bench udp_seg_a inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .z1(z1) ); endmodule

Figure 6.18 Test bench for the module of Figure 6.17.

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x1x2x3x4 = 0000, z1 = 1 x1x2x3x4 = 0001, z1 = 0 x1x2x3x4 = 0010, z1 = 1 x1x2x3x4 = 0011, z1 = 1 x1x2x3x4 = 0100, z1 = 0 x1x2x3x4 = 0101, z1 = 1 x1x2x3x4 = 0110, z1 = 1 x1x2x3x4 = 0111, z1 = 1 x1x2x3x4 = 1000, z1 = 1 x1x2x3x4 = 1001, z1 = 1 x1x2x3x4 = 1010, z1 = 0 x1x2x3x4 = 1011, z1 = 0 x1x2x3x4 = 1100, z1 = 0 x1x2x3x4 = 1101, z1 = 0 x1x2x3x4 = 1110, z1 = 0 x1x2x3x4 = 1111, z1 = 0

Figure 6.19 Outputs for the test bench of Figure 6.18 for the udp_seg_a module of Figure 6.17. The output values match the minterm entries in the Karnaugh map of Fig- ure 6.12. Figure 6.20 Waveforms for the test bench of Figure 6.18 for the udp_seg_a module

• f Figure 6.17.

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//UDP for a 2-input exclusive-OR primitive udp_xor2 (z1, x1, x2); input x1, x2;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 : z1; comment is for readability : 0; 1 : 1; 1 : 1; 1 1 : 0; endtable endprimitive

Figure 6.22 UDP for an exclusive-OR function.

//binary-to-Gray code converter using a UDP module bin_to_gray_udp (b3, b2, b1, b0, g3, g2, g1, g0); input b3, b2, b1, b0;

• utput g3, g2, g1, g0;

//instantiate the udps buf (g3, b3); udp_xor2 (g2, b3, b2); udp_xor2 (g1, b2, b1); udp_xor2 (g0, b1, b0); endmodule

Figure 6.23 Module for a binary-to-Gray code converter using an exclusive-OR UDP.

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//test bench for binary-to-Gray converter module bin_to_gray_udp_tb; reg b3, b2, b1, b0; wire g3, g2, g1, g0; //apply input vectors initial begin: apply_stimulus reg [4:0] invect; for (invect=0; invect<16; invect=invect+1) begin {b3, b2, b1, b0} = invect [4:0]; #10 $display ("b3b2b1b0 = %b, g3g2g1g0 = %b", {b3, b2, b1, b0}, {g3, g2, g1, g0}); end end //instantiate the module into the test bench bin_to_gray_udp inst1 ( .b3(b3), .b2(b2), .b1(b1), .b0(b0), .g3(g3), .g2(g2), .g1(g1), .g0(g0) ); endmodule

Figure 6.24 Test bench for the binary-to-Gray code converter of Figure 6.23.

b3b2b1b0=0000, g3g2g1g0=0000 b3b2b1b0=0001, g3g2g1g0=0001 b3b2b1b0=0010, g3g2g1g0=0011 b3b2b1b0=0011, g3g2g1g0=0010 b3b2b1b0=0100, g3g2g1g0=0110 b3b2b1b0=0101, g3g2g1g0=0111 b3b2b1b0=0110, g3g2g1g0=0101 b3b2b1b0=0111, g3g2g1g0=0100 b3b2b1b0=1000, g3g2g1g0=1100 b3b2b1b0=1001, g3g2g1g0=1101 b3b2b1b0=1010, g3g2g1g0=1111 b3b2b1b0=1011, g3g2g1g0=1110 b3b2b1b0=1100, g3g2g1g0=1010 b3b2b1b0=1101, g3g2g1g0=1011 b3b2b1b0=1110, g3g2g1g0=1001 b3b2b1b0=1111, g3g2g1g0=1000

Figure 6.25 Outputs for the binary-to-Gray code converter of Figure 6.23.

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//UDP for a 2-input exclusive-OR primitive udp_xor2 (z1, x1, x2); input x1, x2;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 : z1; comment is for readability : 0; 1 : 1; 1 : 1; 1 1 : 0; endtable endprimitive

Figure 6.28 Module for the udp_xor2 to be instantiated into the full adder module full_adder_udp.

//full adder using a UDP and built-in primitives module full_adder_udp (a, b, cin, sum, cout); input a, b, cin;

• utput sum, cout;

//define internal nets wire net1, net2, net3; //instantiate the udps and built-in primitive udp_xor2 (net1, a, b); and inst1 (net2, a, b); udp_xor2 (sum, net1, cin); and inst2 (net3, net1, cin);

• r inst3 (cout, net3, net2);

endmodule

Figure 6.29 Module for a full adder using a UDP and built-in primitives.

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//test bench for full adder module full_adder_udp_tb; reg a, b, cin; wire sum, cout; //apply input vectors initial begin: apply_stimulus reg [3:0] invect; for (invect=0; invect<8; invect=invect+1) begin {a, b, cin} = invect [3:0]; #10 $display ("a b cin = %b, sum cout = %b", {a, b, cin}, {sum, cout}); end end //instantiate the module into the test bench full_adder_udp inst1 ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) ); endmodule

Figure 6.30 Test bench for the full adder of Figure 6.29.

a b cin = 000, sum cout = 00 a b cin = 001, sum cout = 10 a b cin = 010, sum cout = 10 a b cin = 011, sum cout = 01 a b cin = 100, sum cout = 10 a b cin = 101, sum cout = 01 a b cin = 110, sum cout = 01 a b cin = 111, sum cout = 11

Figure 6.31 Outputs for the full adder of Figure 6.29.

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//4:1 multiplexer as a UDP primitive udp_mux4 (out, s1, s0, d0, d1, d2, d3); input s1, s0, d0, d1, d2, d3;

• utput out;

table //define state table //inputs are in the same order as the input list // s1 s0 d0 d1 d2 d3 :

• ut comment is for readability

1 ? ? ? : 1; //? is "don't care" ? ? ? : 0; 1 ? 1 ? ? : 1; 1 ? ? ? : 0; 1 ? ? 1 ? : 1; 1 ? ? ? : 0; 1 1 ? ? ? 1 : 1; 1 1 ? ? ? : 0; ? ? : 0; ? ? 1 1 1 1 : 1; endtable endprimitive

Figure 6.33 A UDP for a 4:1 multiplexer.

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//test bench for the 4:1 multiplexer udp module udp_mux4_tb; reg s1, s0, d0, d1, d2, d3; wire out; initial begin //set the input lines to known values d0 = 1; d1 = 0; d2 = 1; d3 = 0; //display the input values #10 $display ("d0=%b, d1=%b, d2=%b, d3=%b \n", d0, d1, d2, d3); // \n is new line //select d0 = 1 s1 = 0; s0 = 0; #10 $display ("s1=%b, s0=%b, output=%b \n", s1, s0, out); //select d1 = 0 s1 = 0; s0 = 1; #10 $display ("s1=%b, s0=%b, output=%b \n", s1, s0, out); //select d2 = 1 s1 = 1; s0 = 0; #10 $display ("s1=%b, s0=%b, output=%b \n", s1, s0, out); //select d3 = 0 s1 = 1; s0 = 1; #10 $display ("s1=%b, s0=%b, output=%b \n", s1, s0, out); #10 $stop; end //instantiate the module into the test bench. //if instantiating only the primitive with no module, //then instantiation must be done using positional notation udp_mux4 inst1 (out, s1, s0, d0, d1, d2, d3); endmodule

Figure 6.34 Test bench for the UDP 4:1 multiplexer.

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d0=1, d1=0, d2=1, d3=0 s1=0, s0=0, output=1 s1=0, s0=1, output=0 s1=1, s0=0, output=1 s1=1, s0=1, output=0

Figure 6.35 Outputs for the UDP 4:1 multiplexer. Page 251 Figure 6.36 Waveforms for the UDP 4:1 multiplexer of Figure 6.33.

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//a 2:1 multiplexer as a udp primitive udp_mux2 (out, s0, d0, d1); input s0, d0, d1;

• utput out;

//define state table table //inputs are in the same order as the input list // s0 d0 d1 :

• ut;

//comment is for readability ? : 0; 1 ? : 1; 1 ? : 0; 1 ? 1 : 1; ? : 0; ? 1 1 : 1; endtable endprimitive

Figure 6.38 A UDP for a 2:1 multiplexer.

//8:1 multiplexer using two 4:1 multiplexer udps //and one 2:1 multiplexer UDP module mux8 (sel, d0, d1, d2, d3, d4, d5, d6, d7, z1); input [2:0] sel; input d0, d1, d2, d3, d4, d5, d6, d7;

• utput z1;

//instantiate the mux udps udp_mux4 inst1 (net1, sel[1], sel[0], d0, d1, d2, d3); udp_mux4 inst2 (net2, sel[1], sel[0], d4, d5, d6, d7); udp_mux2 inst3 (z1, sel[2], net1, net2); endmodule

Figure 6.39 Design module for an 8:1 multiplexer using UDPs.

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//test bench for 8:1 multiplexer module mux8_tb; reg [2:0] sel; reg d0, d1, d2, d3, d4, d5, d6, d7; wire z1; initial begin //set the data input lines to known values d0=1; d1=0; d2=1; d3=0; d4=0; d5=1; d6=0; d7=1; //display the input values #0 $display ("d0=%b, d1=%b, d2=%b, d3=%b, d4=%b, d5=%b, d6=%b, d7=%b", d0, d1, d2, d3, d4, d5, d6, d7); //select d0=1 sel=3'b000; #10 $display ("sel=%b, z1=%b", sel, z1); //select d1=0 sel=3'b001; #10 $display ("sel=%b, z1=%b", sel, z1); //select d2=1 sel=3'b010; #10 $display ("sel=%b, z1=%b", sel, z1); //select d3=0 sel=3'b011; #10 $display ("sel=%b, z1=%b", sel, z1); //select d4=0 sel=3'b100; #10 $display ("sel=%b, z1=%b", sel, z1); //select d5=1 sel=3'b101; #10 $display ("sel=%b, z1=%b", sel, z1); //select d6=0 sel=3'b110; #10 $display ("sel=%b, z1=%b", sel, z1); //continued on next page

Figure 6.40 Test bench for the 8:1 multiplexer of Figure 6.39.

//select d7=1 sel=3'b111; #10 $display ("sel=%b, z1=%b", sel, z1); #10 $stop; end //instantiate the module into the test bench mux8 inst1 ( .sel(sel), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7), .z1(z1) ); endmodule Chapter 6 User-Defined Primitives 19

Figure 6.40 (Continued) Page 254

d0=1, d1=0, d2=1, d3=0, d4=0, d5=1, d6=0, d7=1 sel=000, z1=1 sel=001, z1=0 sel=010, z1=1 sel=011, z1=0 sel=100, z1=0 sel=101, z1=1 sel=110, z1=0 sel=111, z1=1

Figure 6.41 Outputs for the test bench of Figure 6.40 for the 8:1 multiplexer of Fig- ure 6.39.

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//a 3-input OR gate as a udp primitive udp_or3 (z1, x1, x2, x3); input x1, x2, x3;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 x3 : z1; //comment is for readability : 0; 1 : 1; 1 : 1; 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 1; endtable endprimitive

Figure 6.44 UDP for a 3-input OR gate.

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//a 4-input OR gate as a udp primitive udp_or4 (z1, x1, x2, x3, x4); input x1, x2, x3, x4;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 x3 x4 : z1; comment is for readability : 0; 1 : 1; 1 : 1; 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 1; 1 : 1; 1 1 : 1; 1 1 : 1; 1 1 1 : 1; 1 1 : 1; 1 1 1 : 1; 1 1 1 : 1; 1 1 1 1 : 1; endtable endprimitive

Figure 6.45 UDP for a 4-input OR gate.

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//a 4-input AND gate as a udp primitive udp_and4 (z1, x1, x2, x3, x4); input x1, x2, x3, x4;

• utput z1;

//define state table table //inputs are in the same order as the input list // x1 x2 x3 x4 : z1; comment is for readability : 0; 1 : 0; 1 : 0; 1 1 : 0; 1 : 0; 1 1 : 0; 1 1 : 0; 1 1 1 : 0; 1 : 0; 1 1 : 0; 1 1 : 0; 1 1 1 : 0; 1 1 : 0; 1 1 1 : 0; 1 1 1 : 0; 1 1 1 1 : 1; endtable

Figure 6.46 UDP for a 4-input AND gate.

module pos_udp (x1, x2, x3, x4, x5, z1); input x1, x2, x3, x4, x5;

• utput z1;

//define internal nets wire net1, net2, net3, net4; //instantiate the udps udp_or3 inst1 (net1, ~x1, ~x2, ~x3); udp_or3 inst2 (net2, x1, x2, x4); udp_or4 inst3 (net3, ~x1, x3, x4, x5); udp_or4 inst4 (net4, ~x1, ~x3, x4, ~x5); udp_and4 inst5 (z1, net1, net2, net3, net4); endmodule

Page 258 Figure 6.47 Design module for a product-of-sums expression using UDPs.

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//test bench for sum-of products expression using udps module pos_udp_tb; reg x1, x2, x3, x4, x5; wire z1; //apply input vectors initial begin: apply_stimulus reg [5:0] invect; for (invect=0; invect<32; invect=invect+1) begin {x1, x2, x3, x4, x5} = invect [5:0]; #10 $display ("x1x2x3x4x5 = %b, z1 = %b", {x1, x2, x3, x4, x5}, z1); end end //instantiate the module into the test bench pos_udp inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .x5(x5), .z1(z1) ); endmodule

Figure 6.48 Test bench for the product-of-sums expression of Figure 6.47.

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x1x2x3x4x5 = 00000, z1 = 0 x1x2x3x4x5 = 00001, z1 = 0 x1x2x3x4x5 = 00010, z1 = 1 x1x2x3x4x5 = 00011, z1 = 1 x1x2x3x4x5 = 00100, z1 = 0 x1x2x3x4x5 = 00101, z1 = 0 x1x2x3x4x5 = 00110, z1 = 1 x1x2x3x4x5 = 00111, z1 = 1 x1x2x3x4x5 = 01000, z1 = 1 x1x2x3x4x5 = 01001, z1 = 1 x1x2x3x4x5 = 01010, z1 = 1 x1x2x3x4x5 = 01011, z1 = 1 x1x2x3x4x5 = 01100, z1 = 1 x1x2x3x4x5 = 01101, z1 = 1 x1x2x3x4x5 = 01110, z1 = 1 x1x2x3x4x5 = 01111, z1 = 1 x1x2x3x4x5 = 00000, z1 = 0 x1x2x3x4x5 = 00001, z1 = 0 x1x2x3x4x5 = 00010, z1 = 1 x1x2x3x4x5 = 00011, z1 = 1 x1x2x3x4x5 = 00100, z1 = 0 x1x2x3x4x5 = 00101, z1 = 0 x1x2x3x4x5 = 00110, z1 = 1 x1x2x3x4x5 = 00111, z1 = 1 x1x2x3x4x5 = 01000, z1 = 1 x1x2x3x4x5 = 01001, z1 = 1 x1x2x3x4x5 = 01010, z1 = 1 x1x2x3x4x5 = 01011, z1 = 1 x1x2x3x4x5 = 01100, z1 = 1 x1x2x3x4x5 = 01101, z1 = 1 x1x2x3x4x5 = 01110, z1 = 1 x1x2x3x4x5 = 01111, z1 = 1 x1x2x3x4x5 = 10000, z1 = 0 x1x2x3x4x5 = 10001, z1 = 1 x1x2x3x4x5 = 10010, z1 = 1 x1x2x3x4x5 = 10011, z1 = 1 x1x2x3x4x5 = 10100, z1 = 1 x1x2x3x4x5 = 10101, z1 = 0 x1x2x3x4x5 = 10110, z1 = 1 x1x2x3x4x5 = 10111, z1 = 1 x1x2x3x4x5 = 11000, z1 = 0 x1x2x3x4x5 = 11001, z1 = 1 x1x2x3x4x5 = 11010, z1 = 1 x1x2x3x4x5 = 11011, z1 = 1 x1x2x3x4x5 = 11100, z1 = 0 x1x2x3x4x5 = 11101, z1 = 0 x1x2x3x4x5 = 11110, z1 = 0 x1x2x3x4x5 = 11111, z1 = 0

Figure 6.49 Outputs for the product-of-sums expression of Figure 6.47 obtained from the test bench of Figure 6.48.

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//logic circuit using a multiplexer udp //together with other logic gate udps module mux4_mev (x1, x2, x3, x4, E, z1); input x1, x2, x3, x4, E;

• utput z1;

//instantiate the udps udp_and2 inst1 (net1, ~x4, E); udp_xor2 inst2 (net2, x3, x4); udp_and2 inst3 (net3, x3, ~E); udp_or2 inst4 (net4, x4, net3); //the mux inputs are: s1, s0, d0, d1, d2, d3 udp_mux4 inst5 (z1, x1, x2, net1, ~x3, net2, net4); endmodule

Figure 6.53 Module for the logic diagram of Figure 6.52.

//test bench for mux4_mev module mux4_mev_tb; reg x1, x2, x3, x4, E; wire z1; initial //apply input vectors begin: apply_stimulus reg [5:0] invect; for (invect=0; invect<32; invect=invect+1) begin {x1, x2, x3, x4, E} = invect [5:0]; #10 $display ("x1x2x3x4E = %b, z1 = %b", {x1, x2, x3, x4, E}, z1); end end //continued on next page

Figure 6.54 Test bench for Figure 6.53 for the logic diagram of Figure 6.52.

//instantiate the module into the test bench mux4_mev inst1 ( .x1(x1), .x2(x2), .x3(x3), .x4(x4), .E(E), .z1(z1) ); endmodule Chapter 6 User-Defined Primitives 26

Figure 6.54 (Continued) Page 264

x1x2x3x4E = 00000, z1 = 0 x1x2x3x4E = 00001, z1 = 1 x1x2x3x4E = 00010, z1 = 0 x1x2x3x4E = 00011, z1 = 0 x1x2x3x4E = 00100, z1 = 0 x1x2x3x4E = 00101, z1 = 1 x1x2x3x4E = 00110, z1 = 0 x1x2x3x4E = 00111, z1 = 0 x1x2x3x4E = 01000, z1 = 1 x1x2x3x4E = 01001, z1 = 1 x1x2x3x4E = 01010, z1 = 1 x1x2x3x4E = 01011, z1 = 1 x1x2x3x4E = 01100, z1 = 0 x1x2x3x4E = 01101, z1 = 0 x1x2x3x4E = 01110, z1 = 0 x1x2x3x4E = 01111, z1 = 0 x1x2x3x4E = 10000, z1 = 0 x1x2x3x4E = 10001, z1 = 0 x1x2x3x4E = 10010, z1 = 1 x1x2x3x4E = 10011, z1 = 1 x1x2x3x4E = 10100, z1 = 1 x1x2x3x4E = 10101, z1 = 1 x1x2x3x4E = 10110, z1 = 0 x1x2x3x4E = 10111, z1 = 0 x1x2x3x4E = 11000, z1 = 0 x1x2x3x4E = 11001, z1 = 0 x1x2x3x4E = 11010, z1 = 1 x1x2x3x4E = 11011, z1 = 1 x1x2x3x4E = 11100, z1 = 1 x1x2x3x4E = 11101, z1 = 0 x1x2x3x4E = 11110, z1 = 1 x1x2x3x4E = 11111, z1 = 1

Figure 6.56 Outputs obtained from the test bench of Figure 6.54 for the module of Figure 6.53.

Chapter 6 User-Defined Primitives 27

Page 266

//a gated latch as a level-sensitive udp primitive udp_latch_level (q, data, clk, rst_n); input data, clk, rst_n;

• utput q;

reg q; //q is internal storage initial q = 0; //initialize output q to 0 table //define state table //inputs are in the same order as the input list // data clk rst_n : q : q+; q+ is next state ? ? : ? : 0; //latch is reset 1 : ? :

• ;

//- means no change 1 1 : ? : 0; //data=0; clk=1; q+=0 1 1 : ? :

• ;

1 1 1 : ? : 1; //data=1; clk=1; q+=1 ? 1 : ? :

• ;

endtable endprimitive

Figure 6.59 Module for a level-sensitive gated latch UDP.

//test bench for level-sensitive latch module udp_latch_level_tb; reg data, clk, rst_n; wire q; initial //display variables $monitor ("rst_n=%b, data=%b, clk=%b, q=%b", rst_n, data, clk, q); initial //apply input vectors begin #0 rst_n=1'b0; data=1'b0; clk=1'b0; #10 rst_n=1'b1; data=1'b1; clk=1'b1; #10 rst_n=1'b1; data=1'b1; clk=1'b0; #10 rst_n=1'b1; data=1'b0; clk=1'b1; #10 rst_n=1'b1; data=1'b1; clk=1'b1; end //instantiation must be done by position, not by name udp_latch_level inst1 (q, data, clk, rst_n); endmodule

Page 267 Figure 6.60 Test bench for the level-sensitive gated latch of Figure 6.59.

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Page 268

rst_n=0, data=0, clk=0, q=0 rst_n=1, data=1, clk=1, q=1 rst_n=1, data=1, clk=0, q=1 rst_n=1, data=0, clk=1, q=0 rst_n=1, data=1, clk=1, q=1

Figure 6.61 Outputs for the level-sensitive gated latch of Figure 6.59. Figure 6.62 Waveforms for the level-sensitive latch of Figure 6.59.

Chapter 6 User-Defined Primitives 29

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//an 8-bit register designed from a level-sensitive //latch that is modeled as a udp module reg8_udp (clk, rst_n, d, q); input clk, rst_n; input [7:0] d;

• utput [7:0] q;

//instantiate the udps udp_latch_level inst7 (q[7], d[7], clk, rst_n); udp_latch_level inst6 (q[6], d[6], clk, rst_n); udp_latch_level inst5 (q[5], d[5], clk, rst_n); udp_latch_level inst4 (q[4], d[4], clk, rst_n); udp_latch_level inst3 (q[3], d[3], clk, rst_n); udp_latch_level inst2 (q[2], d[2], clk, rst_n); udp_latch_level inst1 (q[1], d[1], clk, rst_n); udp_latch_level inst0 (q[0], d[0], clk, rst_n); endmodule

Figure 6.64 Module for the 8-bit register of Example 6.12 using a level-sensitive latch as a UDP. Page 270

//test bench for the 8-bit register using //level-sensitive latches module reg8_udp_tb; reg clk, rst_n; reg [7:0] d; wire [7:0] q; initial //display variables $monitor ("rst_n=%b, clk=%b, d=%b, q=%b", rst_n, clk, d, q); initial //apply input vectors begin #0 rst_n=1'b0; clk=1'b0; d=8'b0000_0000; #10 rst_n=1'b1; clk=1'b1; d=8'b0101_0101; #10 rst_n=1'b1; clk=1'b0; d=8'b1010_1010; #10 rst_n=1'b1; clk=1'b1; d=8'b1010_1010; #10 rst_n=1'b1; clk=1'b0; d=8'b1111_0000; #10 rst_n=1'b1; clk=1'b1; d=8'b1111_0000; #10 rst_n=1'b1; clk=1'b0; d=8'b0000_1111; #10 rst_n=1'b1; clk=1'b1; d=8'b0000_1111; #10 $stop; end //continued on next page

Figure 6.65 Test bench for the 8-bit register of Figure 6.64.

//instantiate the module into the test bench reg8_udp inst1 ( .rst_n(rst_n), .clk(clk), .d(d), .q(q) ); endmodule Chapter 6 User-Defined Primitives 30

Figure 6.65 (Continued)

rst_n=0, clk=0, d=00000000, q=00000000 rst_n=1, clk=1, d=01010101, q=01010101 rst_n=1, clk=0, d=10101010, q=01010101 rst_n=1, clk=1, d=10101010, q=10101010 rst_n=1, clk=0, d=11110000, q=10101010 rst_n=1, clk=1, d=11110000, q=11110000 rst_n=1, clk=0, d=00001111, q=11110000 rst_n=1, clk=1, d=00001111, q=00001111

Page 271 Figure 6.66 Outputs for the test bench of Figure 6.65 for the 8-bit register of Figure 6.64. Figure 6.67 Waveforms for the 8-bit register of Figure 6.64.

Chapter 6 User-Defined Primitives 31

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//a positive-edge-sensitive D flip-flop primitive udp_dff_edge1 (q, d, clk, rst_n); input d, clk, rst_n;

• utput q;

reg q; //q is internal storage //initialize q to 0 initial q = 0; //define state table table //inputs are in the same order as the input list // d clk rst_n : q : q+; q+ is the next state (01) 1 : ? : 0; //(01) is rising edge 1 (01) 1 : ? : 1; //rst_n = 1 means no rst 1 (0x) 1 : 1 : 1; //(0x) is no change (0x) 1 : : 0; ? (?0) 1 : ? :

• ;

//ignore negative edge //reset case when rst_n is 0 and clk has any transition ? (??) : ? : 0; //rst_n = 0 means reset //reset case when rst_n is 0. d & clk can be anything, q+=0 ? ? : ? : 0; //reset case when 0 --> 1 transition on rst_n. Hold q+ state ? ? (01) : ? :

• ;

//non-reset case when d has any trans, but clk has no trans (??) ? 1 : ? :

• ;

//clk = ?, means no edge endtable endprimitive

Figure 6.69 Primitive module for a positive-edge-sensitive D flip-flop.

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//test bench for the positive-edge-triggered D flip-flop module udp_dff_edge1_tb; reg d, clk, rst_n; wire q; //display variables initial $monitor ("rst_n=%b, d=%b, clk=%b, q=%b", rst_n, d, clk, q); //apply input vectors initial begin #0 rst_n=1'b0; d=1'b0; clk=1'b0; #10 rst_n=1'b1; d=1'b1; #2 clk=1'b1; #10 rst_n=1'b1; d=1'b1; #2 clk=1'b0; #10 rst_n=1'b1; d=1'b0; #2 clk=1'b1; #10 rst_n=1'b1; d=1'b1; #2 clk=1'b0; #10 rst_n=1'b1; d=1'b1; #2 clk=1'b1; #10 rst_n=1'b1; d=1'b0; #2 clk=1'b0; #10 $stop; end //instantiation must be done by position, not by name udp_dff_edge1 inst1 (q, d, clk, rst_n); endmodule

Figure 6.70 Test bench for the D flip-flop primitive module of Figure 6.69. Page 274

rst_n=0, d=0, clk=0, q=0 rst_n=1, d=1, clk=0, q=0 rst_n=1, d=1, clk=1, q=1 rst_n=1, d=1, clk=0, q=1 rst_n=1, d=0, clk=0, q=1 rst_n=1, d=0, clk=1, q=0 rst_n=1, d=1, clk=1, q=0 rst_n=1, d=1, clk=0, q=0 rst_n=1, d=1, clk=1, q=1 rst_n=1, d=0, clk=1, q=1 rst_n=1, d=0, clk=0, q=1

Figure 6.71 Outputs for the positive-edge-sensitive D flip-flop primitive module of Figure 6.69.

Chapter 6 User-Defined Primitives 33

Page 274 Figure 6.72 Waveforms for the positive-edge-sensitive D flip-flop primitive module

• f Figure 6.69.

Page 279

//a modulo-8 counter using an edge-sensitive udp //for a D flip-flop module ctr_mod8_udp1 (clk, rst_n, y1, y2, y3); input clk, rst_n;

• utput y1, y2, y3;

//instantiate the udp logic gates //for the input logic of the counter udp_and2 inst1 (net1, y1, ~y2); udp_and2 inst2 (net2, y1, ~y3); udp_and3 inst3 (net3, ~y1, y2, y3); udp_xor2 inst4 (net4, y2, y3); udp_or3 inst5 (net5, net1, net2, net3); //instantiate the udp D flip-flops //the D flip-flop inputs are: d, clk, rst_n udp_dff_edge1 inst6 (y1, net5, clk, rst_n); udp_dff_edge1 inst7 (y2, net4, clk, rst_n); udp_dff_edge1 inst8 (y3, ~y3, clk, rst_n); endmodule

Figure 6.76 Module for the modulo-8 counter using combinational UDPs and edge- sensitive UDPs.

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//test bench for the modulo-8 counter using a udp //for a D flip-flop module ctr_mod8_udp1_tb; reg clk, rst_n; wire y1, y2, y3; //display variables initial $monitor ("{y1 y2 y3} = %b", {y1, y2, y3}); //generate reset initial begin #0 rst_n = 1'b1; #2 rst_n = 1'b0; #5 rst_n = 1'b1; end //generate clock initial begin clk = 1'b0; forever #10 clk = ~clk; end //determine length of simulation initial begin repeat (10) @ (posedge clk); $stop; end //instantiate the module into the test bench ctr_mod8_udp1 inst1 ( .clk(clk), .rst_n(rst_n), .y1(y1), .y2(y2), .y3(y3) ); endmodule

Figure 6.77 Test bench for the modulo-8 counter of Figure 6.76.

Chapter 6 User-Defined Primitives 35

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{y1 y2 y3} = 000 {y1 y2 y3} = 001 {y1 y2 y3} = 010 {y1 y2 y3} = 011 {y1 y2 y3} = 100 {y1 y2 y3} = 101 {y1 y2 y3} = 110 {y1 y2 y3} = 111 {y1 y2 y3} = 000 {y1 y2 y3} = 001

Figure 6.78 Outputs for the modulo-8 counter of Figure 6.76 for the logic diagram

• f Figure 6.75.

Figure 6.79 Waveforms for the modulo-8 counter of Figure 6.76.

Chapter 6 User-Defined Primitives 36

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//a parallel-in, parallel-out register that shifts right and //rotates right module shift_rotate_udp1 (rst_n, clk, load, d, y); input rst_n, clk, load; input [3:0] d;

• utput [3:0] y;

//flip-flop inputs are: q, d, clk, rst_n //instantiate flip-flop y[3] ******************************* udp_not inst1 (net1, load); udp_and2 inst2 (net2, load, d[3]); udp_and2 inst3 (net3, net1, y[0]); udp_or2 inst4 (net4, net2, net3); udp_dff_edge1 inst5 (y[3], net4, clk, rst_n); //instantiate flip-flop y[2] ******************************* udp_and2 inst6 (net6, load, d[2]); udp_and2 inst7 (net7, net1, y[3]); udp_or2 inst8 (net8, net6, net7); udp_dff_edge1 inst9 (y[2], net8, clk, rst_n); //instantiate flip-flop y[1] ******************************* udp_and2 inst10 (net10, load, d[1]); udp_and2 inst11 (net11, net1, y[2]); udp_or2 inst12 (net12, net10, net11); udp_dff_edge1 inst13 (y[1], net12, clk, rst_n); //instantiate flip-flop y[0] ******************************* udp_and2 inst14 (net14, load, d[0]); udp_and2 inst15 (net15, net1, y[1]); udp_or2 inst16 (net16, net14, net15); udp_dff_edge1 inst17 (y[0], net16, clk, rst_n); endmodule

Figure 6.81 Module for the shift-rotate register of Figure 6.80.

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//test bench for the shift-rotate register module shift_rotate_udp1_tb; reg rst_n, clk, load; reg [3:0] d; wire [3:0] y; //display variables initial $monitor ("y = %b", y); //define reset initial begin #0 rst_n = 1'b0; load = 1'b0; #2 rst_n = 1'b1; load = 1'b1; d = 4'b1100; #4 load = 1'b0; end //generate clock initial begin clk = 1'b0; forever #5 clk = ~clk; end initial //determine length of simulation begin repeat (8) @ (posedge clk); $stop; end //instantiate the module into the test bench shift_rotate_udp1 inst1 ( .rst_n(rst_n), .clk(clk), .load(load), .d(d), .y(y) ); endmodule

Figure 6.82 Test bench for the shift-rotate register module of Figure 6.81.

Chapter 6 User-Defined Primitives 38

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y = 0000 y = 1100 y = 0110 y = 0011 y = 1001 y = 1100 y = 0110 y = 0011 y = 1001

Figure 6.83 Outputs for the shift-rotate test bench of Figure 6.82 for the module of Figure 6.81. Figure 6.84 Waveforms for the shift-rotate test bench of Figure 6.82 for the module

• f Figure 6.81.

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//synchronous Moore state machine module moore1_udp (clk, rst_n, x1, x2, y1, y2, y3, z1, z2, z3); input clk, rst_n, x1, x2;

• utput y1, y2, y3, z1, z2, z3;

//D flip-flop ports are: q, d, clk, rst_n //instantiate the udps for flip-flop y1 udp_or2 inst1 (net1, y2, y3); udp_dff_edge1 inst2 (y1, net1, clk, rst_n); udp_not inst3 (net3, y1); //instantiate the udps for flip-flop y2 udp_and3 inst4 (net4, net3, net8, x1); udp_and3 inst5 (net5, net3, y2, ~x2); udp_or2 inst6 (net6, net4, net5); udp_dff_edge1 inst7 (y2, net6, clk, rst_n); udp_not inst8 (net8, y2); //instantiate the udps for flip-flop y3 udp_and3 inst9 (net9, net3, y2, x2); udp_or2 inst10 (net10, net4, net9); udp_dff_edge1 inst11 (y3, net10, clk, rst_n); udp_not inst12 (net12, y3); //instantiate the output logic udp_and3 inst13 (z1, net3, net8, net12); udp_and3 inst14 (z2, y1, net8, y3); udp_and3 inst15 (z3, y1, y2, net12); endmodule

Figure 6.89 Design module for the Moore machine of Example 6.16.

Chapter 6 User-Defined Primitives 40

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//test bench for the Moore state machine module moore1_udp_tb; reg x1, x2, clk, rst_n; wire y1, y2, y3, z1, z2, z3; //display variables initial $monitor ("x1=%b, x2=%b, y1y2y3=%b, z1z2z3=%b", x1, x2, {y1, y2, y3}, {z1, z2, z3}); //define reset initial begin #0 rst_n = 1'b0; //reset #5 rst_n = 1'b1; //no reset end //define clock initial begin clk = 1'b0; forever #10 clk = ~clk; end //define input sequence initial begin x1 = 1'b0; x2 = 1'b0; @ (posedge clk) //go to state_a (000) //assert z1 x1 = 1'b1; x2 = 1'b0; @ (posedge clk) //go to state_b (011) x2 = 1'b1; x1 = 1'b0; @ (posedge clk) //go to state_c (101) //assert z2 x2 = 1'b1; x1 = 1'b0;//sequence is independent of x1, x2 @ (posedge clk) //go to state_e (100) //continued on next page

Figure 6.90 Test bench for the synchronous Moore machine of Example 6.16.

x1 = 1'b1; x2 = 1'b0;//sequence is independent of x1, x2 @ (posedge clk) //go to state_a (000) //assert z1 x1 = 1'b1; x2 = 1'b0; @ (posedge clk) //go to state_b (011) x2 = 1'b0; x1 = 1'b0; @ (posedge clk) //go to state_d (110) //assert z3 x1 = 1'b0; x2 = 1'b0;//sequence is independent of x1, x2 @ (posedge clk) //go to state_e (100) x2 = 1'b0; x1 = 1'b1;//sequence is independent of x1, x2 @ (posedge clk) //go to state_a (000) //assert z1 #10 $stop; end //instantiate the module into the test bench moore1_udp inst1 ( .clk(clk), .rst_n(rst_n), .x1(x1), .x2(x2), .y1(y1), .y2(y2), .y3(y3), .z1(z1), .z2(z2), .z3(z3) ); endmodule Chapter 6 User-Defined Primitives 41

Figure 6.90 (Continued)

Chapter 6 User-Defined Primitives 42

Page 290

x1=0, x2=0, y1y2y3=000, z1z2z3=100 x1=1, x2=0, y1y2y3=000, z1z2z3=100 x1=0, x2=1, y1y2y3=011, z1z2z3=000 x1=0, x2=1, y1y2y3=101, z1z2z3=010 x1=1, x2=0, y1y2y3=100, z1z2z3=000 x1=1, x2=0, y1y2y3=000, z1z2z3=100 x1=0, x2=0, y1y2y3=011, z1z2z3=000 x1=0, x2=0, y1y2y3=110, z1z2z3=001 x1=1, x2=0, y1y2y3=100, z1z2z3=000 x1=1, x2=0, y1y2y3=000, z1z2z3=100

Figure 6.91 Outputs for the synchronous Moore machine of Example 6.16. Page 291 Figure 6.92 Waveforms for the synchronous Moore machine of Example 6.16.