Verilog HDL:Digital Design and Modeling Chapter 10 Tasks and - - PDF document

Chapter 10 Tasks and Functions 1

Verilog HDL:Digital Design and Modeling Chapter 10 Tasks and Functions

Chapter 10 Tasks and Functions 2

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//module to illustrate a task module task_arith_log; reg [7:0] a, b, c; reg [7:0] z1, z2, z3, z4; initial begin a=8'b0000_1111; b=8'b0011_1100; c=8'b0101_0101; calc (a, b, c, z1, z2, z3, z4); //invoke task a=8'b1111_1111; b=8'b0000_1100; c=8'b1011_1101; calc (a, b, c, z1, z2, z3, z4); //invoke task a=8'b0011_1100; b=8'b0001_1101; c=8'b1010_0101; calc (a, b, c, z1, z2, z3, z4); //invoke task a=8'b1100_1001; b=8'b1011_1101; c=8'b0111_0111; calc (a, b, c, z1, z2, z3, z4); //invoke task end task calc; input [7:0] a, b, c;

• utput [7:0] z1, z2, z3, z4;

begin z1 = (a + b) & (c); z2 = (a + b) | (c); z3 = (a & b) + (c); z4 = (a | b) + (c); $display ("a=%b, b=%b, c=%b, z1=%b, z2=%b, z3=%b, z4=%b", a, b, c, z1, z2, z3, z4); end endtask endmodule

Figure 10.1 Module for the task of Example 10.1.

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a=00001111, b=00111100, c=01010101, z1=01000001, z2=01011111, z3=01100001, z4=10010100 a=11111111, b=00001100, c=10111101, z1=00001001, z2=10111111, z3=11001001, z4=10111100 a=00111100, b=00011101, c=10100101, z1=00000001, z2=11111101, z3=11000001, z4=11100010 a=11001001, b=10111101, c=01110111, z1=00000110, z2=11110111, z3=00000000, z4=01110100

Figure 10.2 Outputs for the task module of Figure 10.2.

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//module to illustrate a task for logical operations module task_logical; reg [7:0] a, b; reg [7:0] a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b; initial begin a=8'b1010_1010; b=8'b1100_1100; logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b); //invoke the task a=8'b1110_0111; b=8'b1110_0111; logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b); //invoke the task a=8'b0000_0111; b=8'b0000_0111; logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b); //invoke the task a=8'b0101_0101; b=8'b1010_1010; logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b); //invoke the task end task logical; input [7:0] a, b;

• utput [7:0] a_and_b, a_nand_b, a_or_b, a_nor_b,

a_xor_b, a_xnor_b; begin a_and_b = a & b; a_nand_b = ~(a & b); a_or_b = a | b; a_nor_b = ~(a | b); a_xor_b = a ^ b; a_xnor_b = ~(a ^ b); $display ("a=%b, b=%b, a_and_b=%b, a_nand_b=%b, a_or_b=%b, a_nor_b=%b, a_xor_b=%b, a_xnor_b=%b", a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b); end endtask endmodule

Figure 10.5 Module for the task of Example 10.2.

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a=10101010, b=11001100, a_and_b=10001000, a_nand_b=01110111, a_or_b=11101110, a_nor_b=00010001, a_xor_b=01100110, a_xnor_b=10011001 a=11100111, b=11100111, a_and_b=11100111, a_nand_b=00011000, a_or_b=11100111, a_nor_b=00011000, a_xor_b=00000000, a_xnor_b=11111111 a=00000111, b=00000111, a_and_b=00000111, a_nand_b=11111000, a_or_b=00000111, a_nor_b=11111000, a_xor_b=00000000, a_xnor_b=11111111 a=01010101, b=10101010, a_and_b=00000000, a_nand_b=11111111, a_or_b=11111111, a_nor_b=00000000, a_xor_b=11111111, a_xnor_b=00000000

Figure 10.6 Outputs for the task module of Figure 10.5.

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//module to illustrate the use of a task module task1_adder4; integer a, b, cin, sum; initial begin a=2; b=5; cin=0; add (a, b, cin, sum); //invoke the task a=3; b=2; cin=1; add (a, b, cin, sum); //invoke the task a=4; b=6; cin=1; add (a, b, cin, sum); //invoke the task a=14; b=63; cin=1; add (a, b, cin, sum); //invoke the task a=150; b=225; cin=0; add (a, b, cin, sum); //invoke the task end task add; input a; input b; input cin;

• utput sum;

integer a, b, cin, sum; begin sum = a + b + cin; $display ("a=%d, b=%d, cin=%d, sum=%d", a, b, cin, sum); end endtask endmodule

Figure 10.8 Module for the task of Example 10.3.

a = 2, b = 5, cin = 0, sum = 7 a = 3, b = 2, cin = 1, sum = 6 a = 4, b = 6, cin = 1, sum = 11 a = 14, b = 63, cin = 1, sum = 78 a = 150, b = 225, cin = 0, sum = 375

Figure 10.9 Outputs for the task module of Figure 10.8.

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//module to illustrate a function module fctn_parity; reg [15:0] addr; reg parity; initial begin parity = calc_parity (16’b1111_0000_1111_0000); if (parity ==1) $display ("parity is even"); else $display ("parity is odd"); parity = calc_parity (16’b1111_0000_1111_0001); if (parity ==1) $display ("parity is even"); else $display ("parity is odd"); end function calc_parity; input [15:0] address; begin calc_parity = ^address; end endfunction endmodule

Figure 10.11 Module for the function of Example 10.4.

parity is even parity is odd

Figure 10.12 Outputs for the function module of Figure 10.11.

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//module to illustrate a function module fctn_count1s; reg [3:0] count; //invoke the function initial begin count = count1s (8'b1100_0011); $display ("number of 1s = %d", count); count = count1s (8'b1101_0011); $display ("number of 1s = %d", count); count = count1s (8'b1111_1011); $display ("number of 1s = %d", count); count = count1s (8'b1010_1010); $display ("number of 1s = %d", count); count = count1s (8'b0000_0000); $display ("number of 1s = %d", count); count = count1s (8'b0000_0010); $display ("number of 1s = %d", count); count = count1s (8'b1111_1111); $display ("number of 1s = %d", count); count = count1s (8'b0110_0100); $display ("number of 1s = %d", count); end //continue on next page

Figure 10.13 Module for a function to count the number of 1s in a word.

function [3:0] count1s; input [7:0] reg_a; reg [3:0] cnt; begin cnt = 0; while (reg_a) begin cnt = cnt + reg_a[0]; reg_a = reg_a >> 1; end count1s = cnt; end endfunction endmodule Chapter 10 Tasks and Functions 9

Figure 10.13 (Continued)

number of 1s = 4 number of 1s = 5 number of 1s = 7 number of 1s = 4 number of 1s = 0 number of 1s = 1 number of 1s = 8 number of 1s = 3

Figure 10.14 Outputs for a function to count the number of 1s in a word.

//module for a full adder using a function module fctn_full_add; reg a, b, cin; reg [1:0] sum; initial begin sum = full_add (1'b0, 1'b0, 1'b0); //invoke the function $display ("abcin=000, cout, sum = %b", sum); sum = full_add (1'b0, 1'b0, 1'b1); $display ("abcin=001, cout, sum = %b", sum); //continued on next page

Page 594 Figure 10.16 Module for the full adder function of Example 10.6.

sum = full_add (1'b0, 1'b1, 1'b0); $display ("abcin=010, cout, sum = %b", sum); sum = full_add (1'b0, 1'b1, 1'b1); $display ("abcin=011, cout, sum = %b", sum); sum = full_add (1'b1, 1'b0, 1'b0); $display ("abcin=100, cout, sum = %b", sum); sum = full_add (1'b1, 1'b0, 1'b1); $display ("abcin=101, cout, sum = %b", sum); sum = full_add (1'b1, 1'b1, 1'b0); $display ("abcin=110, cout, sum = %b", sum); sum = full_add (1'b1, 1'b1, 1'b1); $display ("abcin=111, cout, sum = %b", sum); end function [2:0] full_add; input a, b, cin; reg [1:0] sum; begin case ({a,b,cin}) 3'b000: sum = 2'b00; 3'b001: sum = 2'b01; 3'b010: sum = 2'b01; 3'b011: sum = 2'b10; 3'b100: sum = 2'b01; 3'b101: sum = 2'b10; 3'b110: sum = 2'b10; 3'b111: sum = 2'b11; default:sum = 2'bxx; endcase full_add = sum; end endfunction endmodule Chapter 10 Tasks and Functions 10

Figure 10.16 (Continued)

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abcin=000, cout, sum = 00 abcin=001, cout, sum = 01 abcin=010, cout, sum = 01 abcin=011, cout, sum = 10 abcin=100, cout, sum = 01 abcin=101, cout, sum = 10 abcin=110, cout, sum = 10 abcin=111, cout, sum = 11

Figure 10.17 Outputs for the full adder function module of Figure 10.16.

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//module for a shifter using a function module fctn_shifter; reg [7:0] left_word, right_word; reg ctrl; initial begin left_word = shift (8'b1010_1010, 1'b0);//invoke function $display ("word = %b", left_word); right_word = shift (8'b1100_0011, 1'b1); $display ("word = %b", right_word); left_word = shift (8'b0000_1111, 1'b0); $display ("word = %b", left_word); right_word = shift (8'b0000_1111, 1'b1); $display ("word = %b", right_word); left_word = shift (8'b0010_0000, 1'b0); $display ("word = %b", left_word); right_word = shift (8'b0010_0000, 1'b1); $display ("word = %b", right_word); end function [7:0] shift; input [7:0] word; input ctrl; begin shift = (ctrl == 1'b0) ? (word << 1) : (word >> 1); end endfunction endmodule

Figure 10.18 Module for a function to shift a word left or right 1 bit position.

word = 01010100 word = 01100001 word = 00011110 word = 00000111 word = 01000000 word = 00010000

Page 597 Figure 10.19 Outputs for the shift function module of Figure 10.18.

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//module for an arithmetic and logic unit using a function module fctn_alu; reg [7:0] a, b; reg [1:0] mode; reg [15:0] rslt; initial begin rslt = alu (8'b0000_1111, 8'b0000_0011, 2'b00); $display ("add, a=0000_1111, b=0000_0011, rslt = %b", rslt); rslt = alu (8'b0011_1101, 8'b0010_0011, 2'b00); $display ("add, a=0011_1101, b=0010_0011, rslt = %b", rslt); rslt = alu (8'b0000_1111, 8'b0000_0011, 2'b01); $display ("sub, a=0000_1111, b=0000_0011, rslt = %b", rslt); rslt = alu (8'b0000_1111, 8'b0001_0000, 2'b01); $display ("sub, a=0000_1111, b=0001_0000, rslt = %b", rslt); rslt = alu (8'b0000_1111, 8'b0000_0011, 2'b10); $display ("mul, a=0000_1111, b=0000_0011, rslt = %b", rslt); rslt = alu (8'b0000_1111, 8'b0001_1001, 2'b10); $display ("mul, a=0000_1111, b=0001_1001, rslt = %b", rslt); rslt = alu (8'b0000_1111, 8'b0000_0011, 2'b11); $display ("div, a=0000_1111, b=0000_0011, rslt = %b", rslt); rslt = alu (8'b0011_0111, 8'b0000_0111, 2'b11); $display ("div, a=0011_0111, b=0000_0111, rslt = %b", rslt); end //continued on next page

Figure 10.21 Module to implement a function for a 4-operation ALU.

function [15:0] alu; input [7:0] a, b; input [1:0] mode; reg [15:0] rslt; begin case (mode) 2'b00: rslt = a + b; 2'b01: rslt = a - b; 2'b10: rslt = a * b; 2'b11: rslt = a / b; default: rslt = 16'bxxxx_xxxx_xxxx_xxxx; endcase alu = rslt; end endfunction endmodule Chapter 10 Tasks and Functions 14

Figure 10.21 (Continued) Page 599

add, a=0000_1111, b=0000_0011, rslt = 0000000000010010 add, a=0011_1101, b=0010_0011, rslt = 0000000001100000 sub, a=0000_1111, b=0000_0011, rslt = 0000000000001100 sub, a=0000_1111, b=0001_0000, rslt = 1111111111111111 mul, a=0000_1111, b=0000_0011, rslt = 0000000000101101 mul, a=0000_1111, b=0001_1001, rslt = 0000000101110111 div, a=0000_1111, b=0000_0011, rslt = 0000000000000101 div, a=0011_0111, b=0000_0111, rslt = 0000000000000111

Figure 10.22 Outputs for Figure 10.21, which implements a 4-operation ALU.

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