Verilog 2 - Design Examples 6.375 Complex Digital Systems Arvind - PowerPoint PPT Presentation

Verilog 2 - Design Examples 6.375 Complex Digital Systems Arvind February 9, 2009 Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-1

Verilog can be used at several levels A common approach is to High-Level Behavioral use C/C++ for initial behavioral modeling, and for building test rigs Register Transfer Level automatic tools to synthesize a low-level gate-level model Gate Level Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-2

Writing synthesizable Verilog: Combinational logic Use continuous assignments ( assign ) assign C_in = B_out + 1; Use always@(*) blocks with blocking assignments ( = ) always blocks allow always @(*) more expressive control begin structures, though not out = 2’d0; all will synthesize if (in1 == 1) out = 2’d1; default else if (in2 == 1) out = 2’d2; end Every variable should have a default value to avoid inadvertent introduction of latches Do not assign the same variable from more than one always block – ill defined semantics Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-3

Writing synthesizable Verilog: Sequential logic Use always @(posedge clk) and non- blocking assignments ( <= ) always @( posedge clk ) C_out <= C_in; Use only positive-edge triggered flip-flops for state Do not assign the same variable from more than one always block – ill defined semantics Do not mix blocking and non-blocking assignments Only leaf modules should have functionality; use higher-level modules only for wiring together sub-modules Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-4

An example A B C wire A_in, B_in, C_in; reg A_out, B_out, C_out; +1 +1 always @( posedge clk ) begin A_out <= A_in; B_out <= A_out + 1; The order of non-blocking C_out <= B_out + 1; end assignments does not matter! The effect of non-blocking assignments is not visible until the end of the “simulation tick” Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-5

Another way A B C wire A_in, B_in, C_in; reg A_out, B_out, C_out; +1 +1 always @( posedge clk ) begin A_out <= A_in; B_out <= B_in; B_in and C_in are C_out <= C_in; end evaluated as needed assign B_in = A_out + 1; assign C_in = B_out + 1; Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-6

An example: Some wrong solutions A B C wire A_in, B_in, C_in; reg A_out, B_out, C_out; +1 +1 always @( posedge clk ) begin A_out <= A_in; B_out <= B_in; C_out <= C_in; assign B_in = A_out + 1; Syntactically illegal assign C_in = B_out + 1; end Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-7

Another style – multiple always blocks wire A_in, B_in, C_in; A B C reg A_out, B_out, C_out; always @( posedge clk ) +1 +1 A_out <= A_in; assign B_in = A_out + 1; Does it have the same always @( posedge clk ) functionality? B_out <= B_in; Yes. But why? assign C_in = B_out + 1; Need to understand always @( posedge clk ) something about C_out <= C_in; Verilog execution semantics Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-8

Yet another style – blocking assignments A B C wire A_in, B_in, C_in; reg A_out, B_out, C_out; +1 +1 always @( posedge clk ) begin 1 A_out = A_in; 3 B_out = B_in; Does it have the same 5 C_out = C_in; functionality? end Not even close! 2 assign B_in = A_out + 1; 4 assign C_in = B_out + 1; +1 +1 Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-9

Verilog execution semantics - Driven by simulation - Explained using event queues Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-10

Execution semantics of Verilog - 1 wire A_in, B_in, C_in; Active Event Queue reg A_out, B_out, C_out; always @( posedge clk ) A C B A A_out <= A_in; 1 assign B_in = A_out + 1; always @( posedge clk ) B On clock edge all B_out <= B_in; those events which 2 are sensitive to the assign C_in = B_out + 1; clock are added to always @( posedge clk ) C the active event C_out <= C_in; queue in any order! Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-11

Execution semantics of Verilog - 2 wire A_in, B_in, C_in; Active Event Queue reg A_out, B_out, C_out; always @( posedge clk ) A C 1 B C B A A_out <= A_in; 1 assign B_in = A_out + 1; A evaluates and as a always @( posedge clk ) B consequence 1 is B_out <= B_in; added to the event 2 assign C_in = B_out + 1; queue always @( posedge clk ) C C_out <= C_in; Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-12

Execution semantics of Verilog -3 wire A_in, B_in, C_in; Active Event Queue reg A_out, B_out, C_out; always @( posedge clk ) A 1 2 C 1 C B A_out <= A_in; 1 assign B_in = A_out + 1; Event queue is emptied B evaluates and as a always @( posedge clk ) B B_out <= B_in; consequence 2 is added before we go to next to the event queue clock cycle 2 assign C_in = B_out + 1; always @( posedge clk ) C C_out <= C_in; Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-13

Non-blocking assignment Within a “simulation tick” all RHS variables are read first and all the LHS variables are updated together at the end of the tick Consequently, two event queues have to be maintained – one keeps the computations to be performed while the other keeps the variables to be updated Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-14

Non-blocking assignments require two event queues wire A_in, B_in, C_in; Active Event Queue reg A_out, B_out, C_out; C B A always @( posedge clk ) A 2 1 R R R A_out <= A_in; 1 assign B_in = A_out + 1; Non-Blocking Queue always @( posedge clk ) B B_out <= B_in; C B A L L L 2 assign C_in = B_out + 1; Variables in RHS of always always @( posedge clk ) C blocks are not updated until C_out <= C_in; all inputs (e.g. LHS + dependencies) are evaluated Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-15

Verilog Design Examples Greatest Common Divisor Unpipelined SMIPSv1 processor Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-16

GCD in C int GCD( int inA, int inB) { int done = 0; int A = inA; Such a GCD description can be int B = inB; easily written in Behavioral while ( !done ) Verilog { if ( A < B ) { swap = A; It can be simulated but it will A = B; B = swap; have nothing to do with } hardware, i.e. it won’t else if ( B != 0 ) synthesize. A = A - B; else done = 1; } return A; } Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-17

Behavioral GCD in Verilog module GCD_behav#( parameter W = 16 ) ( input [W-1:0] inA, inB, output [W-1:0] out ); User sets the input reg [W-1:0] A, B, out, swap; operands and checks integer done; always @(*) the output; the begin answer will appear done = 0; A = inA; B = inB; immediately, like a while ( !done ) begin combinational circuit if ( A < B ) swap = A; A = B; B = swap; Note data dependent loop, “done” else if ( B != 0 ) A = A - B; else done = 1; end Courtesy of Arvind http:// out = A; end endmodule February 9, 2009 csg.csail.mit.edu/6.375/ L03-18

Deriving an RTL model for GCD module gcdGCDUnit_behav#( parameter W = 16 ) ( input [W-1:0] inA, inB, output [W-1:0] out ); What does the RTL reg [W-1:0] A, B, out, swap; implementation need? integer done; always @(*) begin State done = 0; A = inA; B = inB; while ( !done ) begin Less-Than Comparator if ( A < B ) swap = A; A = B; B = swap; Equal Comparator else if ( B != 0 ) A = A - B; Subtractor else done = 1; end Courtesy of Arvind http:// out = A; end endmodule February 9, 2009 csg.csail.mit.edu/6.375/ L03-19

Step 1: Design an appropriate port interface input_available result_rdy idle result_taken operand_A result_data operand_B clk reset Courtesy of Arvind http:// February 9, 2009 csg.csail.mit.edu/6.375/ L03-20

Step 2: Design a datapath which has the functional units zero? lt A = inA; B = inB; A while ( !done ) sub begin if ( A < B ) swap = A; B A = B; B = swap; else if (B != 0) A = A - B; else done = 1; End Courtesy of Arvind http:// Y = A; February 9, 2009 csg.csail.mit.edu/6.375/ L03-21

Step 3: Add the control unit to sequence the datapath Control unit should be designed to be either busy or waiting for input or A A B B sel en sel en waiting for B=0 A<B output to be picked up zero? lt A = inA; B = inB; A while ( !done ) sub begin if ( A < B ) swap = A; B A = B; B = swap; else if (B != 0) A = A - B; else done = 1; End Courtesy of Arvind http:// Y = A; February 9, 2009 csg.csail.mit.edu/6.375/ L03-22