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Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 1 (November 26, 2000 6:48 pm)

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CMOS Processing Technology P-well process: Similar to n-well process except a p-well is implanted rather than an n- well. Produces n- and p-transistors that are more balanced. Transistors that reside in the native substrate tend to have better characteristics. In general, p-devices are lower gain than n-devices. Therefore, p-well process naturally moderate the differences.

n-substrate p-w ell lightly doped p-w ell region for n-transistors

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 2 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Twin-tub process: Allows independent optimization of gain, threshold voltage, etc. of n- type and p-type devices. Both types of substrate contacts are REQUIRED in this process.

n+ n+ n+ p+ p+ p+ p-well n+ substrate epitaxial layer n-well

High purity silicon grown with accurately determined dopant concentrations

Epitaxy:

VDD GND

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 3 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Silicon-On-Insulator (SOI) process: Instead of silicon substrate, use an insulating substrate. Silicon can be grown on: Sapphire or SiO2 which in turn has been grown on silicon.

Sapphire lightly doped n-type Si (n-) 1)

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 4 (November 26, 2000 6:48 pm)

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CMOS Processing Technology

Sapphire n- n- Sapphire p- n- p-island Sapphire photoresist Thinox p- n- Sapphire p- n- poly Sapphire Sapphire O xidation + m etalization 2) 3) 4) 5) 6) 7) n-island n- n+ n+ p+ p+ n+ n+

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 5 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Advantages:

• Closer packing of p- and n-transistors, due to absence of wells.
• Absence of latch-up problems (to be discussed).
• Only “sidewall” areas of source and drain diffusions contribute to parasitic

junction capacitance, faster devices.

• Leakage currents to substrate and adjacent devices almost eliminated.
• Enhanced radiation tolerance.

Disadvantages:

• No substrate diodes, inputs more difficult to protect.
• Device gains are lower, I/O structures must be larger.
• Density of contemporary digital processes is actually determined by num-

ber and density of metal interconnection layers.

• Sapphire and silicon on SiO2 substrates are considerably more expensive.

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 6 (November 26, 2000 6:48 pm)

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CMOS Processing Technology CMOS Enhancements:

• More levels of metal interconnect, 2, 3, 4, ...

Eases automated routing and improves power and clock distribution to modules. “Vias” are used to connect upper layers of metal to metal 1. “Contact cuts” are made from metal 1 to diffusion or poly. Aggressive processes allow the stacking of vias on top of contacts. p+ metal 1 contact via metal 2

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 7 (November 26, 2000 6:48 pm)

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CMOS Processing Technology CMOS Enhancements:

• Lower poly sheet resistance.

Poly resistance between 20 and 40 Ohms. If poly combined with a refractory metal, resistance (and delay) can be reduced. Silicide (silicon and tantalum) used as gate material, between 1 and 5 Ohms. Can be extended to source and drain, called salicide (Self ALigned SILI- CIDE). p-substrate Silicide Poly

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 8 (November 26, 2000 6:48 pm)

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CMOS Processing Technology CMOS Enhancements:

• Local interconnect.

Silicide used to make direct connection between poly and diffusion, no contact or metal. e.g. six transistor SRAM cell:

local interconnect m etal 1 p-diff poly V

D D

w

• rd line

bit bit

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 9 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Static memory and analog circuits require passive components: Resistors: Undoped poly; tera ohm values are possible. Capacitors: Second layer of thinox and poly (poly 2). Trench capacitors allow memory densities of 64Mbit and higher. Book covers structures to implement:

• EPROM
• BiCMOS
• thin-film transistors
• 3-D CMOS

We will cover in advanced topics (time permitting).

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 10 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Layout or Design Rules: Design rules specify geometric constraints on the layout artwork. Provide a communication channel between the IC designer and the fab- rication process engineer. Objective: To obtain a circuit with optimum yield. To minimize the area of the circuit. To provide long term reliability of the circuit. Design rules represent the best compromise between performance and yield: More conservative rules increase yield. More aggressive rules increase performance. Design rules represent a tolerance that ensures high probability of cor- rect fabrication - rather than a hard boundary between correct and incorrect fabrication.

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 11 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Layout or Design Rules: Two approaches to describing design rules:

• Lambda-based rules: Allow first order scaling by linearizing the resolu-

tion of the complete wafer implementation. To move a design from 4 micron to 2 micron, simply reduce the value

• f lambda.

Worked well for 4 micron processes down to 1.2 micron processes. However, in general, processes rarely shrink uniformly. Probably not sufficient for submicron processes.

• Micron rules: List of minimum feature sizes and spacings for all masks,

e.g., 3.25 microns for contact-poly-contact (transistor pitch) and 2.75 micron metal 1 contact-to-contact pitch. Micron rules can result in as much as a 50% size reduction over lambda rules. Normal style for industry.

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 12 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Latch-Up: Parasitic circuit effect that causes VDD and GND to short. Can result in self-destruction, at best a malfunction requiring a power cycle. Parasitic bipolar transistors formed between n and p MOS transistors.

n+ n+ p-substrate p+ p+ N PN n-w ell n+ p+ PN P

• ut

in V

D D

G N D

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 13 (November 26, 2000 6:48 pm)

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CMOS Processing Technology Latch-Up: Latch-up is triggered by supply voltage transients which cause VDD to

• vershoot or GND to dip by ~0.7V above or below the supply.

Not likely to occur in core logic. You can prevent this condition by making liberal use of substrate con- tacts:

• Every well MUST have a substrate contact.
• Every substrate contact should be connected to metal directly to a sup-

ply pad.

• Place substrate contacts as close as possible to the source contacts.

I/O circuitry is more susceptible and must be protected.

• Guard rings are used in the I/O pads to reduce gain of parasitic transis-

tors.

• I/O pad design should be left to experts.