Towards a Reconfigurable Nanocomputer Platform Paul Beckett School - - PDF document

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Towards a Reconfigurable Nanocomputer Platform

Paul Beckett School of Electrical and Computer Engineering RMIT University Melbourne, Australia

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The Nanoscale “Cambrian Explosion”

• Disparity:

– Wide range of emerging non-Si technologies

• Diversity:

– Many new device

• ptions in CMOS,

GaAs and other non-Si

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Example Nanoscale Devices

Quantum dot Quantum diffraction FET Quantum interference devices surface super- lattices RSFQ Q-Well GMR/ CMR MQCA Hybrid- Hall effect Molecular nano- magnetics Magnetic RTD Rotaxane molecular x-bar CAEN Coulomb- coupled

• ptically

pumped nanodevices DNA CNT C60 logic & memory Nanotube array logic Large- bandgap devices (AlN, BN) RTD/ HFET RTT logic & memory Multi- valued logic nano- pipelining SOI Si-Ge Dual-gate Vertical FET Ballistic nano-FET Magnetic Molecular Nanotube Hetero- junction Silicon

Disparity → → → →

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The “Ideal” Nanocomputer Platform?

• Very large, scalable with rich, local connectivity
• Built from simple devices that exhibit:

– High functionality (?) – Gain > 1 – Static (at least) and preferably non-volatile operation – (Very) low power density – Room temperature operation

• Reliable and fault tolerant
• Preferably no intrinsic reliance on any form of

global signal (e.g. a master clock)

• Reconfigurable in operation, with little or no

performance penalty

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Three Example Nanoscale Systems

1. Multi-valued SRAM Based Platform

– RTD multi-valued RAM – Dual-gate transistors

• 2. Phase Transition Device Based Platform

– Resistive thin-films

• 3. A Nano-Magnetic Platform

– Double spin-filter junction

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• metal-insulator tunnel

transistor (MITT)

– gate voltage modulates the tunnel barrier

• compatible with current

fabrication processes

– can be buried in oxide layer

• Proposed dual-gate

increases functionality

– Low-overhead reconfiguration

Multi-valued SRAM Based Platform

Drain Source Top Gate Back Gate Tunnel Insulator substrate

gate insulator gate insulator

A

• 0.6
• 0.4
• 0.2

0.0 0.2 0.2 0.4 0.6 0.8 1.0

• 0.4V
• 0.3V
• 0.2V
• 0.1V

0.0V Second-Gate Voltage B C VDD RL VG1 VG2

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Multi-valued SRAM Based Platform

• 3-state memory (Wei & Lin)
• V1-3 matched by adjusting

RTD barrier layer thicknesses

it Line Word Line VDD3 VSS

IP

V1 V2 V3

ID VD IV

VDD3 VSS

VDD VSS VSS VDD

Word Line Bit Line Substrate 1 Substrate 2 RTDs RTDs Out 1

RL RL

insulator Gnd

RL

• Ultimate dimensions

50nm

• ~3 x 109 cells/cm2

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Non-volatility – Chalcogenide Films

• Chalcogenide films act as fast

non-volatile programmable resistor

• Compatible with current

(CMOS) logic fabrication

• Scales well to nanoscale

dimensions (20-30nm)

• Vertical integration

Word Line VA VSS Bit Line Polycrystalline Chalcogenide n p n+ substrate layer bit line ground plane back gate tunnel insulator word line Vdd plane internal routing top gate/input schottky metal

gate insulator gate insulator TiW SiO2

<100nm

Al Heater

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Double Spin-Filter Tunnel Junction

• Magnetoresistive tunnel device (Worledge &

Geballe)

– Potentially very high GMR – Formed from two different layers that are insulating but magnetic with unequal coercivities

nonmagnetic electrode pinned magnetic barrier nonmagnetic electrode free magnetic barrier d d

J Ef J Ef pinned barrier free barrier Antiparallel parallel

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Vertical Double Spin-Filter Junction

• Resistance is varied

between the inner pillar and the multiple outer conductors

• Requires ~20Ǻ films on

vertical pillar

– No obvious candidates

• Thickness control and

lattice matching will be important

Substrate

a) Top View b) Side View “pinned” layer free layer inner conductor

• uter

conductors (x 4) c) Square Mesh Connections

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Spin-Filter Based Platform

• RTD substrate adds

non-linearity to effect logic

• VTT for isolation
• Junction densities in

excess of 2 x 1011/cm2 possible

Conductivesubstrate RTD RTD V

DD

RTD Vertical FET wordline

BL BL BL

tunnel junction

vertical channel gate dielectric

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Spatial Computing

• Memory Hierarchy

– Tries to hide the cost of moving code and data items from one place to another in a processor system

• 3D memory (Zhang)

– Proposed as means memory and processing physically closer together Zhang, 2000

Inter-level Dielectric IC substrate memory layers 3D ROM

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A 3D Reconfigurable Computing Platform

• Merged processor/

memory into 3D structure

• Reduced memory

performance gap

• Extreme memory

bandwidth

• Processing-in-memory;

processing-is-memory

memory/processor layers base substrate vertical interconnect 3D Processor/memory

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Reconfigurable Nanoelectronic Devices?

PRO

• Maximizes utility of

small devices

• Reconfiguration over-

heads kept small

• (Mostly) evolving from

existing techniques

• Compatible with logic

synthesis systems CON

• Can they be built?
• Is the added complexity

justified vs. (say) molecular approach?

• Will they efficiently

support high-performance computer architectures

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What’s Next?

• Simulation of nano-magnetic materials
• Characterization of typical junctions

– e.g. tunneling conductance

• Simulation of GMR-based array platform
• Development of Spatial Computing

techniques suited to this platform

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And in the long term?

• “Decimation followed by diversification”

(Gould)

• Test against the “environment”

– ease of fabrication, cost, ease of use etc.

• Extinction for some, consolidation and

growth for others

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Towards a Reconfigurable Towards a Reconfigurable Nanocomputer Nanocomputer Platform Platform

Thank You Thank You

Paul Beckett Paul Beckett