Total current collapse in High Voltage GaN MIS HEMTs induced by - - PowerPoint PPT Presentation

▶
total current collapse in high voltage gan mis hemts
SMART_READER_LITE
LIVE PREVIEW

Total current collapse in High Voltage GaN MIS HEMTs induced by - - PowerPoint PPT Presentation

Mar 05, 2023 351 likes •596 views

Total current collapse in High Voltage GaN MIS HEMTs induced by Zener trapping Donghyun Jin, J. Joh*, S. Krishnan*, N. Tipirneni*, S. Pendharkar* and J. A. del Alamo * Acknowledgement: SRC, ARPA-E, Samsung Fellowship 1 Current collapse or

slide-1
SLIDE 1

Total current collapse in High‐Voltage GaN MIS‐HEMTs induced by Zener trapping

Donghyun Jin, J. Joh*, S. Krishnan*, N. Tipirneni*,

  • S. Pendharkar* and J. A. del Alamo

Acknowledgement: SRC, ARPA-E, Samsung Fellowship

*

1

slide-2
SLIDE 2

Current collapse or dynamic ON‐resistance in GaN FETs

  • RON depends on device history  After high VOFF, RON ↑↑
  • Big problem in power switching applications

2

slide-3
SLIDE 3

Multi field‐plate (FP) technology

  • Key challenge for current collapse↓↓:

Engineering electric‐field profile at high‐V in the gate‐to‐drain gap of GaN MIS‐HEMTs (Metal‐Insulator‐Semiconductor High‐ Electron‐Mobility Transistors) → Mul field‐plate technology developed G D

AlGaN GaN

Non‐FP FP1 FP2 FP3 G D

AlGaN GaN

Multi‐FP

3

slide-4
SLIDE 4

Multi field‐plate (FP) technology

  • In high‐V OFF‐state,

Non‐FP → intense E‐field peak → current collapse ↑↑ G D

AlGaN GaN

Non‐FP E‐field VG < VT High‐V FP1 FP2 FP3 G D

AlGaN GaN

Multi‐FP

4

slide-5
SLIDE 5

Multi field‐plate (FP) technology

G D

AlGaN GaN

FP1 FP2 FP3 G D

AlGaN GaN

Non‐FP Multi‐FP E‐field E‐field

  • In high‐V OFF‐state,

Non‐FP → intense E‐field peak → current collapse ↑↑ Multi‐FP → depletion region extension and E‐field peak ↓↓ → Effectiveness in current collapse? VG < VT High‐V High‐V VG < VT

5

slide-6
SLIDE 6

Current collapse at high VOFF

GaN MIS‐HEMTs with multi‐FP (FP1,2,3):

  • OFF‐state step‐stress with VDS↑
  • Monitor IDlin (equivalent to RON)

VDS

t

VGS

0 V VT – 5 V 0.2 V

IDlin (VGS= 0 V, VDS= 0.2 V) … … 10 s at every step OFF‐state stress characterization

t

6

slide-7
SLIDE 7

0.2 0.4 0.6 0.8 1 200 400 600 800 IDlin/IDlin(0) VDS_STRESS (V)

RON/RON(0) >1010 VGS= VT – 5 V

Current collapse at high VOFF

GaN MIS‐HEMTs with multi‐FP (FP1,2,3):

  • OFF‐state step‐stress with VDS↑
  • Monitor IDlin (equivalent to RON)

VDS

t

VGS

0 V VT – 5 V 0.2 V

IDlin (VGS= 0 V, VDS= 0.2 V) … … 10 s at every step OFF‐state stress characterization

t

Current collapse

  • Total current collapse for VDS > 300 V
  • RON ↑↑ by > 1010 by VDS= 720 V

7

slide-8
SLIDE 8

Questions to answer

  • Is current collapse recoverable?
  • Where in the device does this happen?
  • What are the dynamics of this process?
  • What is the mechanism responsible?
  • How to mitigate/eliminate?

8

slide-9
SLIDE 9

0.2 0.4 0.6 0.8 1 100 200 300 400 IDlin/IDlin(0) VDS_STRESS (V)

Current collapse recovery?

  • 6 consecutive measurements
  • UV exposure + thermal treatment (180 min at 200oC) in between

OFF‐state stress: VGS=VT‐5 V

Current collapse fully recoverable  trapping! 2nd 1st run 5th 6th 4th 3rd

9

slide-10
SLIDE 10

2 4 6 8 10 12 14 3 6 9 12 15 ID (mA/mm) VDS (V)

After STRESS VGS–VT= 7 V 5 V 3 V

  • 1V

1 V

Lateral extent of current blockage?

Current collapse for low VDS but ID flows again at high VDS punchthrough‐like characteristics  current blockage is short along channel direction Change in output characteristics after VDS=300 V stress for 300 s:

100 200 300 400 500 600 3 6 9 12 15 ID (mA/mm) VDS (V)

Virgin VGS–VT= 7 V 5 V 3 V 1 V After 300 V STRESS

10

slide-11
SLIDE 11

Evolution of subthreshold characteristics and 4 terminal currents:

1.E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00 1.E+02

  • 9.25
  • 7.25
  • 5.25
  • 3.25
  • 1.25

ID (mA/mm) VGS-VT0 (V)

360 V 400 V 300 V 200 V Virgin 100 V

VT0

4 VDS= 0.25 V 500 V 6 2

  • 2
  • No change in VT  current blockage in extrinsic device region
  • At the onset of severe trapping, all currents are negligible

1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 100 200 300 400 ISTRESS (nA/mm) VDS_STRESS (V)

|IG| |IS| |IB| ID

Change in VT and terminal currents?

11

slide-12
SLIDE 12

0.2 0.4 0.6 0.8 1 100 200 300 400 IDlin/IDlin (0) VDS_STRESS (V)

FP1

long short standard

(b)

Impact of device geometry?

Current collapse independent of LGD and geometry of field‐plates

0.2 0.4 0.6 0.8 1 100 200 300 400 IDlin/IDlin (0) VDS_STRESS (V)

LGD

short standard long longer

(a)

0.2 0.4 0.6 0.8 1 100 200 300 400 IDlin/IDlin (0) VDS_STRESS (V)

FP2

long short standard

(c)

0.2 0.4 0.6 0.8 1 100 200 300 400 IDlin/IDlin (0) VDS_STRESS (V)

FP3

short standard long

(d)

12

LFP1 LFP3 LFP2

slide-13
SLIDE 13

Current blockage location?

Channel under field plates fully depleted by VDS=50 V For VDS>50 V, electric field peaks in channel under edge of FP3 Current blockage under edge of FP3 Capacitance‐voltage characteristics of virgin device:

0.2 0.4 0.6 0.8 1 100 200 300 400 CDG/CDG(0) VDS (V)

FP1 FP2 FP3 VGS= VT – 5 V

13

slide-14
SLIDE 14

Role of temperature?

OFF‐state step‐stress at different T:

  • Terminal currents ↑↑ as T↑  Not source of trapping
  • Total current collapse independent of T

 Trapping through tunneling process

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 100 200 300 400

IDlin/IDlin (0) VDS_STRESS (V)

100°C 25°C 200°C VGS= VT – 5 V

(a)

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 100 200 300 400

ID (μA/mm)

VDS_STRESS (V) 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 100 200 300 400

IS (μA/mm) VDS_STRESS (V)

ID

100 °C 25 °C 200 °C 100 °C 25 °C 200 °C

IS

(b)

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 100 200 300 400

IG (μA/mm)

VDS_STRESS (V) 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 100 200 300 400

IB (μA/mm) VDS_STRESS (V)

IG

100 °C 25 °C 200 °C 100 °C 25 °C 200 °C

IB

14

slide-15
SLIDE 15

Dynamics of trapping

Evolution of IDlin during trapping process:

  • Trapping accelerated as VDS_stress↑
  • Characteristic trapping time exhibits Zener‐like dependence
  • n peak electric field under FP3 edge (from simulations)

0.2 0.4 0.6 0.8 1 2 4 6 8 10 IDlin/IDlin(0) Time (min)

180 V 170 V 150 V 160 V 140 V VGS= VT – 5 V

2 4 6 8 10

1 10 100 1000 0.3 0.32 0.34 0.36 τ (sec) 1/EPEAK (cm/MV)

ET – EV ≈ 1 eV

Zener tunneling law:

ln τ

  • 15
slide-16
SLIDE 16

Dynamics of thermal detrapping

Evolution of IDlin during detrapping at different temperatures:

  • Detrapping accelerated as T↑
  • Activation energy: EA= 0.63 eV

OFF‐state stress: VDS_stress= 200 V, t= 600 sec

16 16.5 17 17.5 18 18.5 24 26 28 30

1/kT (eV-1)

EA = 0.63 eV

ln(T2t) (K2s)

16

slide-17
SLIDE 17

0.2 0.4 0.6 0.8 1 5 10 15 20 IDlin/IDlin(0) Time (min)

Dark 2.8 eV 3.1 eV 3.5 eV 4.1 eV Recovery Stress

Dynamics of UV‐enhanced detrapping

Evolution of IDlin during detrapping under UV exposure (300K): Detrapping accelerated by UV with Eh> 2.8 eV

OFF‐state stress: VDS_stress=300 V, t=3 min

17

slide-18
SLIDE 18

Electric field simulations

Silvaco simulations of electric field at top surface of AlGaN barrier from gate to drain:

  • In OFF‐state for VDS> 100 V, field peaks under edge of FP3
  • EPEAK increases with VDS
  • At VDS=200 V, EPEAK= 3.4 MV/cm

1 2 3 4 5 6 7 4 9 14 19 E-field (MV/cm) Space

1000 V 800 V 600 V 400 V 200 V 100 V

EPEAK

Gate FP1 FP2 FP3

1 2 3 4 5 6 7 200 400 600 800 1000 EPEAK (MV/cm) VDS (V)

VGS= VT – 5 V

18

slide-19
SLIDE 19

Summary of key findings

  • Total current collapse after high VOFF bias:

– Fully recoverable – Triggered and accelerated by electric field – Follows Zener‐like dependence with ET–EV= 1.0 eV – Trapped region very short and located under FP3 edge – No effect from variations of LGD and FPs lengths – Temperature independent trapping process – Detrapping enhanced by UV with Eh> 2.8 eV – Detrapping enhanced by temperature with EA= 0.63 eV

19

slide-20
SLIDE 20

Mechanism for total current collapse

Observations consistent with:

  • Field‐induced trapping process  Zener trapping
  • Takes place in narrow region under edge of FP3
  • Electrons from valence band tunnel to traps
  • Trapped electrons lift bands in ON state and create blockage

At high‐VOFF After high‐VOFF

20

slide-21
SLIDE 21

Energy location of traps?

  • From Zener trapping calculations: ET‐EV ≈ 1.0 eV
  • From UV detrapping experiments: Eh ≈ 2.8 eV
  • For reference: Eg(GaN) = 3.4 eV, Eg (Al0.2Ga0.8N) = 3.8 eV

21

slide-22
SLIDE 22

Thermal detrapping with EA=0.63 eV?

If blockage region is short, thermal detrapping possible with E < EC‐ET Thermal detrapping Ea=0.63 eV seems inconsistent with energy picture…

22

slide-23
SLIDE 23

Physical origin of traps?

  • Trap energy consistent with traps responsible for yellow

luminescence in AlGaN and GaN.

  • In GaN: EC‐EYB = 2.5 eV (Calleja, PRB 1997)
  • In Al0.2Ga0.8N: EC‐EYB = 2.8 eV (Hang, JAP 2001)
  • Yellow luminescence traps attributed to C in N site (Lyons,

APL 2010) Mitigation: carefully manage C doping in buffer and migration to AlGaN barrier

23

slide-24
SLIDE 24

Conclusions

  • Total current collapse in high‐voltage GaN MIS‐HEMTs

– Current collapse is recoverable – Attributed to Zener trapping in AlGaN barrier or GaN channel under edge of outermost field plate – Traps are consistent with those responsible for yellow luminescence in GaN and AlGaN – Main suspect: C

  • Attention to defect control during epitaxial growth

and appropriate design of multi field‐plate structures

24