Tim ing Analysis in Presence of Supply Voltage and Tem perature - - PowerPoint PPT Presentation

Tim ing Analysis in Presence of Supply Voltage and Tem perature Variations

Benoît Lasbouygues, Robin W ilson STMicroelectronics, Crolles France Nadine Azem ard, Philippe Maurine LI RMM, Montpellier France

2

Motivation

Delay is strongly dependent on supply voltage

+ 10% Vdd, induce > + 20% delay WC/ BC drop ± 10% of VDD, is it accurate?

Temperature sensitivity depends on domains

Function of process and supply voltage value

• 30
• 15

15 0,8 0,9 1 1,1 1,2

• T. independent

Possibility to reduce m argins Tem perature I nversion VDD(V)

Tim ing ( 1 2 5 ° C-m 4 0 ° C) Tim ing ( 1 2 5 ° C) ( % )

3

Our goal

Reduced margins using “real” V, T values for each cell Avoid over-design or re-design steps How ?

Using Vdrop and T. Gradient maps Non-linear timing derating for each instance

4

Manage Vdd and θ at cell level ?

Popular K-factor method From a standard corner analysis we estimate timing for any Voltage and Temperature value

θ θ ∆ ∂ ∂ + ∆ ∂ ∂ + = D V V D Do Delay

DD DD

Voltage Temperature W orst case Best case Process Voltage Temperature Silicon

How ?

5

Problem

How to define accurately scaling factors?

Linear function not enough accurate Polynomial template not enough accurate on large range of VDD and T.

Scaling must follow physical behavior

θ θ ∆ ∂ ∂ + ∆ ∂ ∂ + = D V V D Do Delay

DD DD

? ?

6

) V ( VDD

) ps (

IN

τ

) V / ps ( VDD

• utHL

∂ ∂τ

Sensitivity analysis

"0.092, 0.247, 0.553, 1.172", \ "0.093, 0.247, 0.556, 1.172", \ "0.103, 0.258, 0.557, 1.166", \ "0.134, 0.275, 0.556, 1.173", \ "0.194, 0.344, 0.597, 1.176" );

Derating factor must characterized:

Slow and Fast domains Design dependence

Transition Tim e LUT I nput slope Output Capacitance

7

Analytical Timing Model – Slope

Modeling the transistor as a current generator Depending on the input range value

Fast input domain: saturation current Slow input domain: current function of slope

MAX DD L

• ut

I V C ⋅ = τ

( )

α

τ

T DD DD L Fast

• ut

V V W K V C DW − ⋅ ⋅ ⋅ ⋅ =

α α α

α τ τ

+ −

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ ⋅ ⋅ ⋅ ⋅ ⋅ =

1 1 1 DD IN L Slow

• ut

W K V C DW

8

Analytical Timing Model – Delay

Propagation Delay is strongly dependent on:

Input slew Output Load Gate size I/ O coupling capacitance (Miller effect)

2 C C C 2 1 V V 2 1 1 t

• ut

L M M DD T IN

τ α α τ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + + + ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + − + =

9

Analytical Timing Model – Temperature

Supply voltage value appears explicitly Temperature acts on Threshold Voltage and Mobility

( )

K

X nom nom nom Tnom T

K K V V ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ = − ⋅ − = θ θ θ θ δ ( ) ( )

α

θ θ δ θ θ τ

nom T DD X nom L Fast

• ut

V V W K C DW

K

− ⋅ + − ⋅ ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ ⋅ =

( )

2 C C C 2 1 V V 2 1 1 t

• ut

L M M DD nom T in

τ θ θ δ α α τ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + + + ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − ⋅ − + − + =

10

Derating Coefficient - VDD

From analytical model,

We derate formulas with respect to VDD We extract design dependency

For slope in fast input domain,

Becomes

aFast, bFast are VDD independent parameters to be calibrated

( )

α

α τ

+

− − ⋅ − ⋅ ⋅ ⋅ = ∂ ∂

1 T DD T DD L DD Fast

• ut

V V V V 1 W K C DW V ) (

L 2 DD Fast Slope 2 DD Fast Slope DD Fast OUT

C V b V a V + = ∂ ∂τ

11

Derating Coefficient – Temperature

Temperature Template

L Fast Delay IN Fast Delay Fast Delay Fast

C c b a t ⋅ + ⋅ + = ∂ ∂ τ θ

L INV INV INinv

C b a ⋅ + = τ

200 400 600 800 1000 1200 1400

• 4 0 ° C

1 2 5 ° C

Delay ( ps) I nput Slope ( ps)

CL= 4 fF CL= 6 4 fF CL= 1 2 0 fF

300 600 900

200 400 600 800 1000 1200 1400

• 4 0 ° C

1 2 5 ° C

• 4 0 ° C

1 2 5 ° C

Delay ( ps) I nput Slope ( ps)

CL= 4 fF CL= 6 4 fF CL= 1 2 0 fF

12

Derating Coefficient – Constraint

Clock Setup Data Setup Setup

c b a Setup τ τ θ ⋅ + ⋅ + = ∂ ∂

Setup and Hold:

Race between Clock and Data paths.

Ignore Load sensitivity, keep only slope variation

Clock CPI Data D1 D2 D3 CPI CPN CPN CPI C1 C2 CPN

Setup = ( D1 + D2 + D3 ) – C1

13

Validation – Standard cell

Template are fitted with 3 corners (1 ref., 1 for Vdd, 1 for T) Corner computed for an entire library with derating factor Comparison: scaling values versus electrical simulations

• 40
• 20

20 40 60 80 100 120 0.8 0.9 1 1.1

• 10
• 5

5 10 15

Tem perature ( ° C) V DD( V) Sim ulation vs Derating ( % ) Ref.

+ 5 %

• 5 %

0 %

14

Application - Chip level

Derating on Slope Com pute delay W ith new slope Derating on Delay

Slope file (~ SDF) Final SDF 1 timing update with new slope New SDF is available (delay can be scaled using internal developed tool) Final annotation is done

15

Application – Chip level

Timing Analysis with Vdrop data From a worst case corner, we update delay with Vdrop maps. We compute each Slope and Delay derating (cell by cell) Comparison : TA with (Vdd – 10% ) Versus : TA with Vdrop Data

Chip Vdrop map IP Vdrop map

16

Results

Comparison Spice/ WC/ Derating

Margin gain : 9 to 12% ~ 200ps

Path Delay ( ns) Path # 9 % 1 2 % 2 % accuracy

1 ,7 5 2 ,0 0 2 ,2 5 2 ,5 0 1 2 3 4 5 6 7 8

W orst case tim ing Derating analysis Spice analysis

17

Summary

We propose a method to handle Temperature/ VDD variations based on cell by cell scaling factor

These deratings are non-linear and function of design conditions

Taking account Vdrop in TA, highlights a significant gain in margin versus standard worst case method. Voltage Derating could be also used to validate Dynamic Voltage, Multi-Voltage feature Method has demonstrated for precise Temperature effects such as Temperature inversion and can be used to characterize hot spots.

18

Thank you !!