The International Semiconductor Roadmap The International - PowerPoint PPT Presentation

The International Semiconductor Roadmap The International Semiconductor Roadmap and Its Impact on Semiconductor- -Related Related and Its Impact on Semiconductor Research Research Jan M. Rabaey Jan M. Rabaey Gigascale Research Center (GSRC) Gigascale Research Center (GSRC

The International Technology RoadMap RoadMap for for The International Technology Semiconductors Semiconductors � Inaugurated in 1992 (as the NTRS). Inaugurated in 1992 (as the NTRS). Initiative of SIA (Semiconductor Industry Initiative of SIA (Semiconductor Industry Association) Association) � Became an International effort in 1997 Became an International effort in 1997 (ITRS) (ITRS) � Provides bi Provides bi- -annual updates on 15 year annual updates on 15 year road- -map map road � Joint effort of industry, government, Joint effort of industry, government, consortia, and universities consortia, and universities � A An assessment of the semiconductor n assessment of the semiconductor technology requirements. The objective of technology requirements . The objective of the ITRS s to ensure advancements in the the ITRS s to ensure advancements in the performance of integrated circuits. performance of integrated circuits. � Identifies the Identifies the technological challenges technological challenges and needs facing the semiconductor and needs facing the semiconductor industry over the next 15 years. industry over the next 15 years . 2

A Typical Roadmap Table A Typical Roadmap Table 3

A Typical Roadmap Table (cntd cntd) ) A Typical Roadmap Table ( 4

More Sophistication over the Years More Sophistication over the Years The “Living” ITRS Roadmap (started in 2001) The “Living” ITRS Roadmap (started in 2001) � Provides: � Provides: consistency checks, unified assumptions for power, consistency checks, unified assumptions for power, frequency, die size, density, performance, etc frequency, die size, density, performance, etc � Creates linkages � Creates linkages between different between different Quantified Power Management � Quantified Power Management areas areas Performance MPU) for -Performance MPU) for � Improves � Improves Design Technology Design Technology flexibility, quality, flexibility, quality, Gap (High - � Gap (High transparency of transparency of roadmapping roadmapping 5

Important Outcome: Challenges and Roadblocks Important Outcome: Challenges and Roadblocks 6

Example: The Productivity Gap Example: The Productivity Gap 10,000,000 100,000,000 Logic Transistors/Chip p .10µ i Transistor/Staff Month h 1,000,000 10,000,000 h C t n r 58%/Yr. compound o 100,000 1,000,000 e M p y Complexity growth rate t s - .35µ i 10,000 100,000 v r f o i f ) t a K t c s t 1,000 10,000 ( u S i s d / . n x o s a 100 1,000 r n x x x r P a T x x r x T c 100 21%/Yr. compound 10 2.5µ i g Productivity growth rate o 10 L 1 1 9 1 3 7 7 9 3 5 7 5 9 3 5 1 9 9 0 0 0 8 8 9 9 9 0 0 8 8 8 9 9 0 0 0 9 9 9 9 9 0 0 9 9 9 1 1 2 2 2 1 1 1 1 1 2 2 1 1 1 Source: SEMATECH 7

Focus Center Research Program Focus Center Research Program Origin of This Program Origin of This Program � Bill Perry � Gordon Moore � Bill Perry � Gordon Moore U.S. Universities--Our National Treasure � Paul Kaminski � Craig Barrett � Paul Kaminski � Craig Barrett Semiconductor Technology Council Co-Chairs � Anita Jones � Larry Sumney � Anita Jones � Larry Sumney OSD/MARCO Agreement � Dan Radack � Harold Hosack � Dan Radack � Harold Hosack DARPA/MARCO Joint Solicitation & Management 8

Industry Motivation Industry Motivation Critical problems accelerate toward us-- --In 2 years time, In 2 years time, Critical problems accelerate toward us the red areas are 3 years closer! the red areas are 3 years closer! 2006 2005 1997 NTRS Tables 1997 NTRS Tables 1999 ITRS Tables 1999 ITRS Tables 100nm 100nm Table 14 Memory and Logic Technology Requirements TWG Technology Requirements Year of First Product Shipment 1997 1999 2001 2003 2006 2009 2012 1999 2002 2005 2008 2011 2014 Technology Generation 250 nm 180 nm 150 nm 130 nm 100 nm 70 nm 50 nm 180 130 nm 100 nm 70 nm 50 nm 35 nm 2.5–1.8 1.8–1.5 1.5 –1.2 1.5 –1.2 1.2–0.9 0.9–0.6 0.6–0.5 Min. Logic V dd (V) (desktop) ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% Min. Logic V dd (V) (desktop) 1.8 - 1.5 1.5 - 1.2 1.2 - 0.9 0.9 - 0.6 0.6 - 0.5 0.6 - 0.3* V dd Variation T ox Equivalent (nm) 4–5 3–4 2–3 2–3 1.5–2 < 1.5 < 1.0 Tox equivalent (nm) 2.-3 1.5-2 <1.5 <1 < 1.0 < 1.0 Equivalent Maximum E-field 4–5 5 5 5 > 5 > 5 > 5 Max I off @ 25 °C (MV/cm) (nA/µm) 5 5 4 3 3 2 1 1 3 3 3 10 10 Max I off @ 25 ° C (nA/µm) (For min. L device) High Perf. (For minimum L device) Nominal I o n @ 25 °C (µA/µm) 750/350 750/350 750/350 750/350 750/350 750/350 Nominal I on @ 25 ° C (µA/µm) 600/280 600/280 600/280 600/280 600/280 600/280 600/280 [NMOS/PMOS] High Perf. Max I off @ 25 °C (NMOS/PMOS) (pA/µm) 10 10 10 10 10 Gate Delay Metric (CV/I) (ps)* 16–17 12–13 10–12 9–10 7 4–5 3–4 4.71E+02 V T 3 σ Variation ( ± 60 50 45 40 40 40 40 (For min. L device) Low Power mV) Nominal I o n @ 25 °C (µA/µm) (For minimum L device) 450/210 450/210 450/210 450/210 450/210 450/210 ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% L gate 3 σ Variation [NMOS/PMOS] Low Power T 3 σ variation (±mV) V (For nominal device) 25 17 17 50 42 33 ≤ 20% ≤ 20% ≤ 20% ≤ 20% ≤ 20% ≤ 20% ≤ 20% (For min. L device) L eff 3 σ Variation S/D extension junction depth, 0.045 - 0.07 0.03 - 0.05 0.025 - 0.04 0.02 - 0.028 0.013 - 0.02 0.01 - 0.014 (For nominal device; % of L eff ) nominal (µm) S/D Extension Junction Depth, 50–100 36–72 30–60 26–52 20–40 15–30 10–20 Nominal (nm) Gate sheet resistance ( Ω /sq) 4 - 6 4 - 6 4 - 6 <5 <5 <5 ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% ≤ 10% Total Series Resistance of S/D @ minimum dimension (% of channel resistance) Gate Sheet Resistance ( Ω /sq) 4–6 4–6 4–6 4–6 4–6 < 5 < 5 Isolation Pitch Consistent with the linear scaling per generation 6--7 7 7--8 8 8-9 9 Interconnect Levels 6 6–7 7 7 7–8 8–9 9 Interconnect Levels Short Wire Pitch (µm) 0.50 –0.75 0.36 –0.54 0.30–0.45 0.26–0.39 0.2–0.3 0.14–0.21 0.10–0.15 DRAM Cell Size (µm 2 ) 0.56 0.22 0.14 0.09 0.036 0.014 0.006 0.07 - Short wire pitch ( µ m) 0.36 - 0.54 0.26 - 0.39 0.2 - 0.3 0.14 - 0.21 0.10 - 0.15 0.11 Soft Error Rate (FITs) 1000 1000 1000 1000 1000 1000 1000 DRAM Retention Time (ms) 64–128 128–256 – 256 –512 512–1024 1024– 2048–4096 0.0074 - DRAM cell size ( µ m 2 ) 0.26 - 0.32 0.13 - 0.17 0.06 - 0.08 0.03 - 0.04 0.015 - 0.02 2048 0.0098 Flash Data Retention (year) 10 10 10 10 10 10 10 Cell Dielectric Tox Equivalent 3.3 - 4.3 1.7 - 2.7 1.15 0.7 - 1.0 0.5 0.4 NOR Cell Size (µm 2 ) 0.6 0.3 0.22 0.15 0.08 0.04 0.02 (nm) 8.5 8 8 7.5 7 6.5 6 +/– V pp 250 220 220 200 200 200 Min. Refresh Time (ms) Tunnel Oxide (nm) 8.5 8 8 7.5 7 6.5 6 Flash Endurance (erase/write 100K 100K 100K 100K 100K 1 0 0 K 1 0 0 K 500 Soft Error rate (fits) cycles) 500 500 500 500 500 ESD Protection Voltage (V/µm) 6 7.5 9 10.5 12 13.5 15 Solutions Exist Solutions Being Pursued No Known Solutions The objective of the FCRP is the establishment of focused multi-university teams to engage in The objective of the FCRP is the establishment of focused multi university teams to engage in * The CV/I gate delay metric is calculated using the data in this table along with the microprocessor gate length given in the ORTC table (Appendix B). The transistor width is assumed to be 5 mm for NMOS and 10 mm for PMOS at the 250 nm generation. Device width is then scaled consistent with minimum feature size scaling. discovery research discovery research in in areas where evolutionary research and development have failed areas where evolutionary research and development have failed to find to find solutions to anticipated problems for the semiconductor industry. solutions to anticipated problems for the semiconductor industry 16 9