The DEPFET pixel detector for BELLE II 8 th International Hiroshima - - PowerPoint PPT Presentation

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The DEPFET pixel detector for BELLE II 8 th International Hiroshima - - PowerPoint PPT Presentation

May 11, 2023 343 likes •641 views

LMU Mnchen - Excellence Cluster Universe The DEPFET pixel detector for BELLE II 8 th International Hiroshima Symposium on Development and Application of Semiconductor Tracking Detectors Stefan Rummel on behalf of the DEPFET Collaboration

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SLIDE 1

LMU München - Excellence Cluster Universe

The DEPFET pixel detector for BELLE II

8th International “Hiroshima” Symposium on Development and Application of Semiconductor Tracking Detectors Stefan Rummel on behalf of the DEPFET Collaboration Stefan.Rummel@lmu.de

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SLIDE 2

DEPFET collaboration

Stefan Rummel 2

  • Charles University, Prague
  • DESY Hamburg
  • IFIC Valencia
  • IFJ PAN, Krakow
  • IHEP, Bejing
  • LMU Munich
  • TU Munich
  • MPI Munich / HLL
  • University of Bonn
  • University of Heidelberg
  • University of Giessen
  • University of Göttingen
  • University of Karlsruhe

DEPFET collaboration was established for ILC-Vertexing, in 2009 moved towards BELLE II DEPFET community still grows!

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SLIDE 3

BELLE II / SuperKEKB – Latest news

Stefan Rummel 3

On 18.11.11:

  • SuperKEKB ground breaking ceremony
  • MoU between KEK and German funding agencies signed
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SLIDE 4

Overview

Stefan Rummel 4

  • Introduction
  • SuperKEKB and BELLE II
  • DEPFET concept
  • Working principle
  • The DEPFET-PXD system
  • R&D
  • Mechanics and services
  • System and DAQ
  • Readout chips
  • Test Beams
  • Power distribution system
  • Requirements
  • System Layout
  • Performance
  • Outlook
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SLIDE 5

SuperKEKB upgrade

Stefan Rummel 5

  • Luminosity / precision frontier

 Looking for new physics in the loops

  • 10.4GeV @ Y(4S) resonance
  • SuperKEKB asymmetric e+/e- collider

 B-Mesons with boost in lab frame

  • Nano beam option + increased current

 Accelerator upgrade to 8x1035 1/cm2/s

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SLIDE 6

BELLE II upgrade

Stefan Rummel 6

  • High luminosity poses challenges

for all sub detectors

  • Upgrade of data acquisition
  • Performance improvements in sub

detectors

  • Inner detector:
  • Silicon strip detector suffers

under high occupancy

  • Two layers of pixel detector

(PXD)

  • In total 6 Silicon layers

Challenges to the PXD:

  • High interaction rate
  • Radiation hardness of ~1 MRad/y
  • High precision

 High readout speed  Low mass, high resolution

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SLIDE 7

The DEPFET - Active Pixel Detector

Stefan Rummel 7

Depleted Field Effect Transistor

  • In pixel amplification of charge
  • Potential minimum under gate
  • Electrons modulate current in FET
  • Charge is removed via clear
  • Low input capacity
  • Fully depleted operation - high sensitive

volume

  • Charge collection always active

 DEPFET allows to build low mass, high S/N detector!

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SLIDE 8

The DEPFET - Technology

Stefan Rummel 8

DEPFET is developed and produced at MPI - Semiconductor lab (HLL) in Munich:

  • Double sided process on high

resistivity silicon

  • Detectors on wafer scale
  • Thinning technology available

 Low leakage current  Flexible size  Low multiple scattering

450mm 50mm

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SLIDE 9

The DEPFET – Matrix

  • peration

Stefan Rummel 9

  • DEPFET pixel cell arranged on grid
  • Readout
  • Rolling shutter mode
  • Correlated Double Sampling / Single Sampling
  • Frame time 20µs – 92ns row processing time

 Column parallel readout – fast readout

 Low power dissipation in active area

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SLIDE 10

BELLE II DEPFET-PXD

Stefan Rummel 10

  • PXD in a nutshell:
  • Radius:

14,22mm

  • Pixel size 50x50µm², 50x75µm²
  • Pixel:

8M

  • Thickness: 75µm
  • Radiation hardness: 10MRad
  • Frame time:

20µs

  • Material budget:

0.2% X0

 DEPFET PXD will significantly improve z- vertex resolution of the inner detector

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SLIDE 11

Mechanical Engineering

Stefan Rummel 11

  • Engineering challenges:
  • Stable mounting - vibration
  • Cooling
  • Services in/out
  • Tight mechanical constraints:
  • Beampipe @ 12mm radius
  • SVD @ 38mm radius
  • Active area cooled by cold air

 Data and heat is generated at the end of module – outside the acceptance!

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SLIDE 12

Mechanical Engineering

Stefan Rummel 12

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SLIDE 13

System layout

Stefan Rummel 13

  • Zero suppression on module level
  • Online pattern recognition to reject

background

  • Online silicon only tracking

~15m ~40cm 4 links @ 1.25Gbit/s ~80Gbit/s ~4Gbit/s

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SLIDE 14

System layout – Readout and steering chips

Stefan Rummel 14

Switcher

Control of gate and clear 32 x 2 channels Switches up to 30V 0.35 µm HV technology

DCDB

Amplification and digitization of DEPFET signals 256 input channels 8-bit ADC per channel 92 ns sampling time 180 nm technology

DHP

Signal processor Common mode correction Pedestal subtraction 0-supression Timing and trigger control 90nm technology

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SLIDE 15

DEPFET test beam

Stefan Rummel 15

  • Testbeam CERN 10/2011:
  • 50µm thin DEPFETS
  • 92ns row processing time
  • DUTs:
  • L=4µm, standard oxide: SNR ~40
  • L=6µm, thin oxide: SNR ~ 20
  • Resolution: 12.4µm

 Full readout speed and first thin DEPFET in TB

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SLIDE 16

Power distribution requirements

Stefan Rummel 16

  • Around 20 voltages are needed
  • Steering/Biasing voltages for the DEPFET
  • Fine tuning for optimization
  • Parameter changes due to irradiation
  • Precise hardware current limit
  • Bipolar and sink/source output needed
  • Low noise essential for SNR
  • Supply voltages for the ASICs
  • Sub-micron chips sensitive to over voltage
  • Sink/source output needed
  • Need control on transient behavior of PS-system
  • Several dependencies between voltages
  • Dedicated power up and down sequences

 Development of a dedicated low noise power supply system

Steering voltages: Frontend voltages:

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SLIDE 17

PS System – Architecture

Stefan Rummel 17

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SLIDE 18

PS System – Low noise

  • peration

Stefan Rummel 18

  • Low noise essential for successful operation
  • Efficiency / spatial resolution
  • dE/dx resolution
  • E.g. Gate_ON voltage: gm~20-40µS  1mVrms  20-40nArms ≈ Frontend noise!

 Low PS noise crucial for PXD operation How to get low noise at module level?

1. Control emission of PS 2. Shield the system from interference 3. Close current loops locally

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SLIDE 19

Stefan Rummel 19

  • PS level
  • Remote sensing with long lines

 Can’t count on PSRR

  • DC/DC converter with broadband filtering
  • Physically separate converter from regulators
  • Additional output filtering
  • Power distribution:
  • Cabling with combined braid/foil shield
  • Common mode and differential mode close to detector
  • Lines sharing a common impedance lead to intrinsic noise due to

varying load current

  • Close current loops locally
  • Assure low output impedance at load for all frequencies

 Project to investigate EMC compatibility on PXD level has been started PS System – Low noise

  • peration
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SLIDE 20

PS System – Output impedance

Stefan Rummel 20

Hierarchical approach – based on available space:

  • Low frequencies ( dc ~ 20kHz):

Regulator is active

  • Mid frequencies (20kHz-~MHz):

Decoupling on PP level

  • High frequencies (>~MHz):

Decoupling on module level

~20nH ~5uH

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SLIDE 21

PS System – Output impedance

Stefan Rummel 21

  • Spice simulation of regulator and

cables

  • Measurement with regulator

 Output impedance is kept low

  • ver a wide frequency range

 Careful layout necessary to control resonances

Amplifier roll off PP Decoupling takes effect Dip: ESR of C and PCB ESL, L(PCB) dominates Module level Takes effect

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SLIDE 22

Summary

Stefan Rummel 22

  • The KEKB accelerator is upgraded towards 8x1035/cm²/s
  • A 2 layer pixel detector based on DEPFET will be installed
  • Design of PXD is well advanced
  • DEPFET pixel cell, radiation hardness
  • Mechanical design and cooling
  • Readout electronics and data acquisition
  • TB program ongoing
  • Readout speed and thin DEPFET sensors demonstrated in test beam
  • Design of a dedicated PS system for the DEPFET PXD is ongoing, first

prototype has been tested

  • PXD ready by mid 2015
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SLIDE 23

Backup

Stefan Rummel 23

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SLIDE 24

Schedule

Stefan Rummel 24

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SLIDE 25

CP – Violation What do we measure?

Stefan Rummel

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Precise Vertex detectors essential to measure CP violation!

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SLIDE 26

Physics motivation

  • NP can visible via loop corrections
  • Suppressed decay of K0 lead to forecast of Charm
  • Top mass was known before discovery
  • Example:

Models with charged Higgs doublet (2HDM-II):

B + → τ + ν Γ(B+ → τ + ν) = ΓSM(B+ → τ + ν) [1-(mb/mH)²tan²ϐ]²

  • Energy reach far beyond Ecms

Stefan Rummel

26 red: 5σ discovery region @5ab-1

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SLIDE 27

Power supply transient response

  • Load transients of readout chips lead to

dangerous overvoltage spikes

  • Limits of overvoltage have been derived for

180nm/90nm technology  Overvoltage can be controlled by capacitors close to the load

Stefan Rummel 27

15m, 2.5A,100nF 15m, 2.5A,10µF 15m, 2.

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SLIDE 28

Thinning Technology

Stefan Rummel 28

sensor wafer sensor wafer handle wafer handle wafer

Wafer bonding SOI process Thinning of top wafer (CMP) Processing etching of handle wafer (structured)