Systems Logic Gates and Electrical Properties Shankar Balachandran* - - PowerPoint PPT Presentation

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Aug 31, 2022 231 likes •393 views

Spring 2015 Week 5 Module 23 Digital Circuits and Systems Logic Gates and Electrical Properties Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay

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Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 5 Module 23

Logic Gates and Electrical Properties

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Logic Gates and Electrical Properties 2

CMOS Transistors

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NMOS and PMOS

Logic Gates and Electrical Properties 3

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CMOS Inverter

in

Vdd (“1”) GND (“0”) 1 1

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CMOS NAND and NOR Gates

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CMOS Inverter Transfer Characteristics

Input Output Vout Vin

0.6 1 1.5 2 2.5 0.6 1 1.5 2 2.5 P on N off P off N on

Vinv Vdd Vdd

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Logic Levels: I/O Voltages

 VIH = min. input voltage for logic 1  VIL = max. input voltage for logic 0  VOH = min. output voltage for logic 1  VOL = max. output voltage for logic 0

VOH VOH VOL VOL VIL VIL VIH VIH Vout Vin

Undefined Region

“1” “0”

slope = -1 slope = -1

Nominal Voltage Levels:

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DC Noise Margins

 Noise margin is a meaningful means for measuring the robustness of a

circuit against noise. VOH VOL VIL VIH

Undefined Region

“1” “0” NMH NML

High State DC Noise Margin: NMH = VOH - VIH Low State DC Noise Margin: NML = VIL - VOL

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Noise Margins in a CMOS Inverter

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Other Properties

 Current: Very little current flows in the gate except while

it is switching.This is why CMOS is used in low power applications such as digital clocks.

 Static Power: Steady state or static power consumption

is negligible and is due to leakage currents. However, for sub-100nm (ultra-deep submicron) CMOS technologies this power is becoming comparable to other power components.

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Capacitances

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Resistance

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 Treat transistor as a resistor  In reality, there are several resistances  Also, resistance values are different in different modes of

peration of a transistor

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Other Properties (contd…)

 Dynamic Power: A CMOS circuit consumes significant power only

during the switching.This is called dynamic power, PD. Dynamic power consumption depends on the total load capacitance, CL, which is to be charged and discharged at the gate output, and the switching frequency.

where, CL = Cload + gate output capacitance + Cwire f = output switching frequency

 Short Circuit Power: This is the other component of power

dissipation which occurs during switching. It is due to the flow of short circuit (or through) current between Vdd and GND.

f V C P

2 DD L D 

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Other Electrical Properties

 Fanout: The number of inputs that are driven by a single

utput is known as the fanout of the output.

 A practical limit on fanout is caused by load (capacitance, CL) on

the gate output which must charge/discharge when signal levels change.

 Fanin: The number of inputs that a gate can have is called

the fanin.

 Higher fanin usually means higher delay (because of transistors in

series)

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End of Week 5: Module 23

Thank You

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