Syed Aftab ab Rashi hid, Geoffrey Nelissen,Eduardo Tovar Task A - - PowerPoint PPT Presentation

Syed Aftab ab Rashi hid, Geoffrey Nelissen,Eduardo Tovar

Processor Data cache L1

• Instr. cache

L1 Cache L2 Main memory

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } 1 2 3 4 5 6 7 8

Task A

Processor Data cache L1

• Instr. cache

L1 Cache L2 Main memory

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } 1 2 3 4 5 6 7 8

Slow Task A

Processor Data cache L1

• Instr. cache

L1 Cache L2 Main memory

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } 1 Int i=0 2 If i < 10 3 fct_B 4 fct_B 5 fct_B 6 fct_B 7 ++i 8 goto 2

Fast Task A

Data cache L1

• Instr. cache

L1 Cache L2 Main memory

The utilisat lisation

• n of caches

ches reduces uces the worst st-case ase execution ecution time me (WCET) ET) of a task sk in isol

• lation

ation

Processor

• Intra-Task Cache Interference
• Inter-Task Cache Interference

• Intra-task Cache Interference

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } fct_C { int j = 0; while(j < 10) { call fct_D( y ); ++j; } }

Task A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Cache

• Intra-task Cache Interference

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } fct_C { int j = 0; while(j < 10) { call fct_D( y ); ++j; } }

Task A

1 Int i=0 2 If i < 10 3 fct_B 4 fct_B 5 fct_B 6 fct_B 7 ++i 8 goto 2 9 10 11 12 13 14 15 16

Cache

• Intra-task Cache Interference

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } fct_C { int j = 0; while(j < 10) { call fct_D( y ); ++j; } }

Task A

1 Int i=0 2 If i < 10 3 fct_B 4 fct_B 5 fct_B 6 fct_B 7 ++i 8 goto 2 9 Int j=0 10 If j < 10 11 fct_D 12 fct_D 13 fct_D 14 fct_D 15 ++j 16 goto 10

Cache

• Intra-task Cache Interference

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } fct_C { int j = 0; while(j < 10) { call fct_D( y ); ++j; } }

Task A

1 Int i=0 2 If i < 10 3 fct_B 4 fct_B 5 fct_B 6 fct_B 7 ++i 8 goto 2 9 Int j=0 10 If j < 10 11 fct_D 12 fct_D

Cache

• Intra-task Cache Interference

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } fct_C { int j = 0; while(j < 10) { call fct_D( y ); ++j; } }

Task A

1 Int i=0 / fct_D 2 If i < 10 / fct_D 3 fct_B / ++j 4 fct_B / goto 10 5 fct_B 6 fct_B 7 ++i 8 goto 2 9 Int j=0 10 If j < 10 11 fct_D 12 fct_D

Cache

• Intra-task Cache Interference

fct_A { int i = 0; while(i < 10) { call fct_B( x ); ++i; } } fct_C { int j = 0; while(j < 10) { call fct_D( y ); ++j; } }

Task A

1 Int i=0 / fct_D 2 If i < 10 / fct_D 3 fct_B / ++j 4 fct_B / goto 10 5 fct_B 6 fct_B 7 ++i 8 goto 2 9 Int j=0 10 If j < 10 11 fct_D 12 fct_D

Cache Intra-ta task sk cach che e interference erence occurs if the memor

• ry footpri

tprint nt of a task is larg rger than the allocat cated ed cache space or when two memory entries es

• f that task are mapped

ed to the same space in cache. Increa ease se in intra-task ask cache he interference erence may also result in increas asing ng the WCET of tasks.

• Inter-task Cache Interference

• Inter-task Cache Interference

–Cache Related Preemption Delays (CRPD) –Cache Persistence Reload Overhead (CPRO)

• Inter-task Cache Interference

–Cache Related Preemption Delays (CRPD)

• Inter-task Cache Interference

–Cache Related Preemption Delays (CRPD)

Task B

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Related Preemption Delays (CRPD)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Related Preemption Delays (CRPD)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Related Preemption Delays (CRPD)

Task A Task B

Cache Related Preemption Delay (CRPD)

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Persistence Reload Overhead (CPRO)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Persistence Reload Overhead (CPRO)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Persistence Reload Overhead (CPRO)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

Shorter response time

• Inter-task Cache Interference

–Cache Persistence Reload Overhead (CPRO)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

• Inter-task Cache Interference

–Cache Persistence Reload Overhead (CPRO)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

Cache Persistence Reload Overhead (CPRO)

• Inter-task Cache Interference

–Cache Related Preemption Delay (CRPD) –Cache Persistence Reload Overhead (CPRO)

Task A Task B

1 2 3 4 5 6 7 8

Cache set

Cache Persistence Reload Overhead (CPRO) Cache Related Preemption Delay (CRPD)

Both CRPD D and CPRO O may result in increa easi sing ng the WCET/W T/WCRT of tasks.

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Sequential Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Sequential Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Sequential Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference Higher Intra- task cache interference

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference Higher Intra- task cache interference

τ1 τ2 τ3

CS Optimized Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference Higher Intra- task cache interference

τ1 τ2 τ3

CS Optimized Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference Higher Intra- task cache interference

τ1 τ2 τ3

CS Optimized Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Full Cache Partitioning

τ1 τ2 τ3

CS Sequential Cache Allocation

Higher Inter- task cache interference Higher Intra- task cache interference

τ1 τ2 τ3

CS Optimized Cache Allocation

Cache Eviction caused by τ1 are inevitable !!!

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Optimized Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Optimized Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Optimized Cache Allocation

• Example: Task set Ƭ={τ1, τ2, τ3} and a cache of total size CS.

τ1 CS τ2 CS/2 τ3 CS/2 τ1 τ2 τ3

CS Optimized Cache Allocation

Task set sched edulabi ulabilit ity may imp mprove e if the reduc ducti tion

• n in the inter

er- task k cache he inter erferen erence ce between τ1 and τ2 dominat minate the incre rease se in the e intra ra-task task cache he inter erferenc rence of τ1 and τ2

1. 1. Cache he Coloring

• ring approach to optimize task layou
• ut in memory

2. 2. Boun unding ing intra- and inter-task cache he inter erfere erenc nce when using cache coloring 3. 3. Cache he Inter erferen rence ce-Aware WCRT Analysis 4. 4. Simulat ated ed An Annealing ealing Algorithm to optimize cache color assignm gnment nt of tasks

• OS

OS-le level el softw tware are technique to contr trol the mapping ing of tasks in cache.

• OS

OS-le level el softw tware are technique to contr trol the mapping ing of tasks in cache.

• Lies

es in the mapping ing between phys ysica cal l addres dress s and cache entr tries ies

Physical Page # (x+y) bits Page offset (z) bits

Physical Address (x+y+z) bits

Cache Set Index

Cache Mapping

Line offset

• OS

OS-le level el softw tware are technique to contr trol the mapping ing of tasks in cache.

• Lies

es in the mapping ing between phys ysica cal l addres dress s and cache entr tries ies

Physical Page # (x) bits Color Index (y) bits Page offset (z) bits

Physical Address (x+y+z) bits

Cache Set Index

Cache Mapping

Line offset

• OS

OS-le level el softw tware are technique to contr trol the mapping ing of tasks in cache.

• Lies

es in the mapping ing between phys ysica cal l addres dress s and cache entr tries ies

Physical Page # (x) bits Color Index (y) bits Page offset (z) bits

Physical Address (x+y+z) bits

1 Task 1 2 Task 1 3 Task 1 4 Task 2 5 Task 2 6 Task 2 7 Task 2 8 Task 2 9 Task 3 10 Task 3 11 Task 3 12 Task 3 13 Task 3 14 Task 3 15 Task 4 16 Task 4

Cache

Color 1 Color 3

Color 2 Color 4

Cache Set Index

Cache Mapping

Line offset

• Intr

tra-ta task sk cache interference depends on the cache space or the num umbe ber

• f cache colors assigned

gned to a task.

• Intr

tra-ta task sk cache interference depends on the cache space or the num umbe ber

• f cache colors assigned

gned to a task.

Var ariati iation

• n in the wo

worst st-case ase exec ecutio tion time and the wo worst st- case se memor mory dema mand d of the benchmark fdct of the Mälardalen benchmark suite

• Intr

tra-ta task sk cache interference depends on the cache space or the num umbe ber

• f cache colors assigned

gned to a task.

𝑫𝒋[𝒍𝒋] = 𝑫𝒋

𝒏𝒋𝒐

Var ariati iation

• n in the wo

worst st-case ase exec ecutio tion time and the wo worst st- case se memor mory dema mand d of the benchmark fdct of the Mälardalen benchmark suite

𝑵𝑬𝒋 𝒍𝒋 = 𝑵𝑬𝒋

𝒏𝒋𝒐

𝑳𝒋 ≥ 𝟓

• Intr

tra-ta task sk cache interference depends on the cache space or the num umbe ber

• f cache colors assigned

gned to a task.

𝑫𝒋[𝒍𝒋] = 𝑫𝒋

𝒏𝒋𝒐

Var ariati iation

• n in the wo

worst st-case ase exec ecutio tion time and the wo worst st- case se memor mory dema mand d of the benchmark fdct of the Mälardalen benchmark suite

𝑵𝑬𝒋 𝒍𝒋 = 𝑵𝑬𝒋

𝒏𝒋𝒐

𝑫𝒋 𝒍𝒋 ≥ 𝑫𝒋

𝒏𝒋𝒐

𝑵𝑬𝒋 𝒍𝒋 ≥ 𝑵𝑬𝒋

𝒏𝒋𝒐

𝑳𝒋 ≥ 𝟓 𝑳𝒋 < 𝟓

• Intr

tra-ta task sk cache interference depends on the cache space or the num umbe ber

• f cache colors assigned

gned to a task.

𝑫𝒋[𝒍𝒋] = 𝑫𝒋

𝒏𝒋𝒐

Var ariati iation

• n in the wo

worst st-case ase exec ecutio tion time and the wo worst st- case se memor mory dema mand d of the benchmark fdct of the Mälardalen benchmark suite

𝑵𝑬𝒋 𝒍𝒋 = 𝑵𝑬𝒋

𝒏𝒋𝒐

𝑫𝒋 𝒍𝒋 ≥ 𝑫𝒋

𝒏𝒋𝒐

𝑵𝑬𝒋 𝒍𝒋 ≥ 𝑵𝑬𝒋

𝒏𝒋𝒐

𝑳𝒋 ≥ 𝟓 𝑳𝒋 < 𝟓

𝑫𝑱𝒋

𝒋𝒐𝒖𝒔𝒃,𝒍𝒋 = 𝑵𝑬𝒋 𝒍𝒋 − 𝑵𝑬𝒋 𝒏𝒋𝒐

• Inter

er-ta task sk Cache he Inter erferenc rence due to CRPDs

• Inter

er-ta task sk Cache he Inter erferenc rence due to CPROs

Cache sets fct_A { some code; int i = 0; while(i < 2) { call fct_B( x ); ++i; } some code; } Task B

×2

• Usefu

eful Cache he Blocks cks (UCB) CB) = cache blocks that are used more than n once e during the execution of a task without eviction

Cache sets

Usef eful l Cach che e Bloc

• cks

fct_A { some code; int i = 0; while(i < 2) { call fct_B( x ); ++i; } some code; } Task B

fct_C { some code; . . . more code; } Cache sets

Evic icting ing Cach che e Bloc

• cks

Task A

• Al

All cache blocks used by a task during its execution are called Ev Evicting ing Cache he Block cks s (EC ECB)

• Number of UCBs

Bs of the preempt pted ed task upper bound the CRPD it can suffer

• Number of ECBs

Bs of the preempti pting task upper bound the CRPD it can cause se

CRPD = intersection between the UCBs of the preempted task and the ECBs of the preempting tasks

ECB UCB

CRPD PD

Preem reempted pted Tasks sks Preem reempting pting Task sks s

fct_C { some code; . . . more code; } Cache sets Task B

Persist istent nt Cache e Blocks

Cache blocks that are once loaded in the cache and will never be evict cted/i ed/invalidat idated ed by the task itself when it executes in in isolation tion are called Persist isten ent t Cach che e Blocks cks (PCB CBs) s)

• Number of PCBs

Bs of a task upper bounds the CPRO O it can suffer er.

• Number of ECBs

Bs of a task upper bounds the cache evicti ctions

• ns it can cause

se

• The intersecti

ection

• n upper-bou
• unds

nds the CPRO

CPRO= intersection between the PCBs of the task under analysis and the ECBs of all the other tasks

ECB PCB

CPRO

Analy lyzed ed Task sk All ll other Task sks s

• Several tasks sharing

ring a cache color, actual set of EC ECBs/UC /UCBs/PCBs PCBs of tasks may not

• t be known.

• Several tasks sharing

ring a cache color, actual set of EC ECBs/UC /UCBs/PCBs PCBs of tasks may not

• t be known.

1 2 3 4

Cache

Color 1

τ1 τ2

For k1=1 =1 , |UCB1|=2 =2 For K2=1, =1, |UCB2|=2 =2

• Several tasks sharing

ring a cache color, actual set of EC ECBs/UC /UCBs/PCBs PCBs of tasks may not

• t be known.

1 2 3 4

Cache

Color 1

τ1 τ2

{UCB1} } = {1,2} 2} {UCB2} } = {3,4} 4} For k1=1 =1 , |UCB1|=2 =2 For K2=1, =1, |UCB2|=2 =2

• Several tasks sharing

ring a cache color, actual set of EC ECBs/UC /UCBs/PCBs PCBs of tasks may not

• t be known.

1 2 3 4

Cache

Color 1

τ1 τ2

For k1=1 =1 , |UCB1|=2 =2 For K2=1, =1, |UCB2|=2 =2 {UCB1} } = {3,4} 4} {UCB2} } = {1,2} 2}

• Several tasks sharing

ring a cache color, actual set of EC ECBs/UC /UCBs/PCBs PCBs of tasks may not

• t be known.

1 2 3 4

Cache

Color 1

{UCB1} = {1,2} or {3,4}… {UCB2} = {3,4} or {1,2}…

τ1 τ2

For k1=1 =1 , |UCB1|=2 =2 For K2=1, =1, |UCB2|=2 =2

• Several tasks sharing

ring a cache color, actual set of EC ECBs/UC /UCBs/PCBs PCBs of tasks may not

• t be known.

1 2 3 4

Cache

Color 1

Different rent set of EC ECBs/UCBs/P /UCBs/PCBs CBs of tasks may lead to different pessim ssimisti tic/op c/opti timis mistic tic value of CRPD/CP /CPRO τ1 τ2

{UCB1} = {1,2} or {3,4}… {UCB2} = {3,4} or {1,2}… For k1=1 =1 , |UCB1|=2 =2 For K2=1, =1, |UCB2|=2 =2

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

1 2 3 4

τi

3 4 5 6

τj

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

1 2 3 4

τi

3 4 5 6

τj

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

1 2 3 4

τi

3 4 5 6

τj

𝑽𝑫𝑪𝒋(𝒍𝒋) 𝑭𝑫𝑪𝒌(𝒍𝒋,𝒌)

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

1 2 3 4

τi

3 4 5 6

τj

𝑽𝑫𝑪𝒋(𝒍𝒋) 𝑭𝑫𝑪𝒌(𝒍𝒋,𝒌)

𝐷𝐽𝑗,𝑘

𝑗𝑜𝑢𝑓𝑠,𝛿 = 𝑛𝑗𝑜{𝑉𝐷𝐶𝑗 𝑙𝑗 , 𝐹𝐷𝐶 𝑘 𝑙𝑗,𝑘 }

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

1 2 3 4

τj

3 4 5 6

τi

𝑸𝑫𝑪𝒌(𝒍𝒌) 𝑭𝑫𝑪𝒋(𝒍𝒌,𝒋

′ )

• Task τjmay only evict cache content of τi if they use the same cache colors
• The number of UCBs/PCBs for a given cache color assignment are known.

1 2 3 4

τj

3 4 5 6

τi

𝑸𝑫𝑪𝒌(𝒍𝒌) 𝑭𝑫𝑪𝒋(𝒍𝒌,𝒋

′ )

𝐷𝐽𝑗,𝑘

𝑗𝑜𝑢𝑓𝑠,𝜍 = 𝑛𝑗𝑜{𝑄𝐷𝐶 𝑘 𝑙𝑘 , 𝐹𝐷𝐶𝑗 𝑙𝑘,𝑗 ′

}

Worst-case execution time of task τi in isolation assuming the cache space allocated to τi is equal to its size in main memory Intra-task cache interference suffered by task τi Intra-task cache interference suffered by the higher priority task τj Total Inter-task cache interference due to CPRO during the response time of task τi Total Inter-task cache interference due to CRPD during the response time of task τi

Objective Function (x) Number of Iterations

Initial Solution Local Optima Global Optima

1

Task 1, Task 4

2

Task 1, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 2

7

Task 2, Task 3

8

Task 3

Cache

1

Task 1, Task 4

2

Task 1, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 2

7

Task 2, Task 3

8

Task 3

Cache

1

Task 2, Task 4

2

Task 2, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 1

7

Task 1, Task 3

8

Task 3

Cache

re_allocate(1,2)

1

Task 1, Task 4

2

Task 1, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 2

7

Task 2, Task 3

8

Task 3

Cache

1

Task 1, Task 4

2

Task 1, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 2

7

Task 3

8

Task 3

Cache

re_size(2)

1

Task 1, Task 4

2

Task 1, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 2

7

Task 2, Task 3

8

Task 3

Cache

1

Task 1, Task 4

2

Task 1, Task 4

3

Task 2

4

Task 2

5

Task 2

6

Task 2

7

Task 3

8

Task 3

Cache

re_size(2)

• Hepta

tane static WCET analysis tool

• l was used to derive task parameters
• Experiments were performed using Mälarda

dalen len benchmark suite.

• A case

se st study udy experiment and empirica irical evaluation using large number of task sets. ets.

• Comp
• mpar

arison ison between the propose

• sed and SOA approaches was performed

by varying ing different parameters.

https://team.inria.fr/alf/software/heptane/

Sequential Cache Color Assignment Full Cache Partitioning

Sequential Cache Color Assignment Full Cache Partitioning SA-based Cache Color Assignment NO re-sizing SA-based Cache Color Assignment with re-sizing

Sequential Cache Color Assignment Full Cache Partitioning SA-based Cache Color Assignment NO re-sizing SA-based Cache Color Assignment with re-sizing Not Schedulable! Not Schedulable! Not Schedulable! Schedulable!

~13% ~11%

Conclusion lusion

• Intra- and inter-task

ask cache interference is interrel elated ed and balan ancin cing their contr tribution ibution to tasks WCRT may result in imp mproving ing task set schedulab edulabilit ity.

• Cach

che e coloring ring approach to optim imize ize task layout ut.

• Bounde

nded the intra- and inter-task ask cache interference under cache coloring.

• Simulat

ated ed Annea ealin ing approach to optimize cache color

• r assignmen

gnment of tasks.

• Experimental evalua

aluati tion n showing the effectiveness our approach

Fut uture ure Work rk

• Presented work assumed a direct mapped cache, in future we plan to exten

end it to N-way set et associa

• ciati

tive caches.

• We also aim to extent this analysis to shared

ed cache in multi ticor core platforms.

Conclusion lusion

• Intra- and inter-task

ask cache interference is interrel elated ed and balan ancin cing their contr tribution ibution to tasks WCRT may result in imp mproving ing task set schedulab edulabilit ity.

• Cach

che e coloring ring approach to optim imize ize task layout ut.

• Bounde

nded the intra- and inter-task ask cache interference under cache coloring.

• Simulat

ated ed Annea ealin ing approach to optimize cache color

• r assignmen

gnment of tasks.

• Experimental evalua

aluati tion n showing the effectiveness our approach

Fut uture ure Work rk

• Presented work assumed a direct mapped cache, in future we plan to exten

end it to N-way set et associa

• ciati

tive caches.

• We also aim to extent this analysis to shared

ed cache in multi ticor core platforms.

Thank You… 