Towards a Time-Predictable Node Peter Puschner slides credits: P. - - PowerPoint PPT Presentation

Towards a Time-Predictable Node

Peter Puschner

slides credits: P. Puschner, R. Kirner, B. Huber

VU 2.0 182.101 SS 2015

Embedded System

Application Computer Communication Unit

ES Component

Communication

W(T) W(T)

task T with time budget W(T)

Task timing is only

• ne out of a number
• f parameters that

determine the timing

• f activities on an

ES component

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From RT Tasks to RT Systems

so far: focus on single task (WCET, predictability) How do we build a complete (distributed) real-time system that is time-predictable?

• Synchronizing with the “real-world clock”
• Network communication and I/O
• Operating system
• Schedulability, scheduling
• Task timing interferences
• WCET assessment of single tasks

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A Time-triggered HRT Subsystem

Application Computer Safety- Critical Connector Unit

HRT Subsystem

• f a Component

Time-Triggered State Message Port Memory Element for a Single State Message Synchronized Clock Control Signal Port Symbols

Time-Triggered Communication

W(T)

Services of the TTA (see RTS lecture)

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TTA Services of Interest

• Synchronized real-time reference clock
• Clock interrupt
• Time-triggered network communication and I/O

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Services we have to look at ...

• Synchronized real-time clock reference
• Clock interrupt
• Time-triggered network communication and I/O
• Operating system
• Schedulability, scheduling
• Task timing interferences
• WCET assessment of single tasks

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OS Software and Scheduling

Remember: take control decisions offline!! Task model: simple tasks, single-path code Operating system structure & scheduling

• Single-path code wherever possible
• Static, table-driven scheduling:

Offline decisions for I/O, comm., task switching and preemption

• Use clock interrupt to synchronize with RT clock

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Static Schedule

Programmable clock interrupt Interrupt: start of defined task chains Statically scheduled preemptions à ??? Statically scheduled I/O and message access

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T1 T2’ T1 T2’’ T3 Clock Interrupt Scheduled preemption T4 ... OS: dispatching, c. switch OS: clock int. handler OS: task switch

• Appl. tasks

T1

Predictable Preemption???

Find a task preemption mechanism with fully predictable task preemption in presence of direct- mapped instruction caches We have to ensure that the HW & SW architecture guarantees convergence of cache behavior (prediction of cache behavior should be easy)

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Variable Timing of Instruction Cache

task 1 { … instr_k; … }

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task 2 { … while (cond) { instr_i; } … }

cache conflict multiple references to same code location (e.g., stmts within loops, multiple calls of a function)

Clock-Driven Task Preemption

System properties:

• Actions of the system take place in a cyclic way
• Tasks Ti are periodic with periods pi
• The duration of a scheduling round is defined as

the least common multiple (lcm) of all task periods Straight-forward solution: è use a timer to trigger task preemption

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Clock-Driven Task Preemption (2)

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Task trace T1 (higher priority) Task trace T2 (lower priority)

Ii Ik Ii’

cache conflict same memory location

Clock-Driven Task Preemption (3)

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T1 T2 T1 T2

Scenario A Scenario B

Ii Ik Ii’ Ii Ik Ii’

instruction timing cache miss penalty

Revised Strategy: Task Preemption by Instruction Count

Task preemption within each scheduling round at statically determined instruction-count instances Realization: instruction-counter interrupt

• hardware register to count the number of

executed instructions (can be reset)

• without HW support, code instrumentations

raising a SW trap could serve the same purpose

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Task Preemption by Instruction Counter

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T1 T2 T1 T2

First cycle All other cycles

Task Preemption by Instruction Counter

Cache State: elements & position in cache Cache Content set of cache: elements in cache We need convergence of cache behavior!

➭ Stable Warmup of instruction cache:

all future executions of a periodically executed fixed instruction sequence will show identical instruction hit/miss patterns.

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Task Preemption by Instruction Counter

Sufficient condition to reach Stable Warmup

• f instruction cache:
• 1. Hit/miss depends only on cache content set, not
• n cache state
• 2. On instruction access: element is placed at a

well-defined position in cache (update of other elements is determined by their

• ld position & current access)
• 3. Each element occurs at most once in the cache

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à Direct-Mapped Instruction Cache

Dealing with Clock Drift

Master clock synchronization

• Programmed clock interrupt from connector unit

Planned variable-size window of inactivity before expected sync. time (needs bound on clock skew)

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clock interrupt fast CPU slow CPU

…

window of inactivity re-synchronization

Composability

Temporal composability is not guaranteed in the presence of shared state (e.g., caches)

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T1: T2: t1(A) t2(A) t1(A) = t2(A)

Example: A and B in a loop; A fills the entire cache; ð cache conflicts between A and B

A A B

?

Prefetch Memory

• Explicit load and store, planned offline
• Consistent with pre-planning of schedules and

pre-determined control flow of single-path code

• Tool support to generate control code
• Benefit from “knowledge of the future”:

prefetching unit always knows the instructions that will be executed next à maximum number of hits

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Prefetch Memory – Analysis

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Prefetch Memory – Control

Instr. ¡ CPU ¡ Data ¡

PF Mem. Prefetch Controller DRAM

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A Time-Predictable Component

Application Computer Safety- Critical Connector Unit

HRT Subsystem

• f a Component

Time-Triggered State Message Port Memory Element for a Single State Message Synchronized Clock Control Signal Port Symbols

Time-Triggered Communication

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Time-Predictable Component (2)

synchronized representation of global time instruction counter “clock”, synchronized to the local representation of global time Data transfer triggered by progression of instruction counter clock Data transfer triggered by progression of global-time representation Programmable clock interrupt to synchronize the instruction- counter clock with the global-time representation Static schedule (instruction-counter interrupt for preemptions)

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Conclusion

We can construct a fully time-predictable node! You only have to observe two clocks and you will know the current action of the computer system:

• 1. CPU clock: controls all steps performed;

ð count ticks to observe progress

• 2. Global-time interrupt: reference point

synchronized with environment ð start counting ticks on the CPU clock when global-time interrupt occurs

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