Towards a Time-Predictable Node Peter Puschner slides credits: P. - PowerPoint PPT Presentation

Towards a Time-Predictable Node Peter Puschner slides credits: P. Puschner, R. Kirner, B. Huber VU 2.0 182.101 SS 2015

Embedded System Task timing is only ES Component Application Computer one out of a number W(T) of parameters that determine the timing of activities on an ES component Communication Unit Communication task T with time budget W(T) W(T) 2

From RT Tasks to RT Systems so far: focus on single task (WCET, predictability) How do we build a complete (distributed) real-time system that is time-predictable? • Synchronizing with the “real-world clock” • Network communication and I/O • Operating system • Schedulability, scheduling • Task timing interferences • WCET assessment of single tasks 3

A Time-triggered HRT Subsystem Application Computer W(T) of a Component HRT Subsystem Symbols Time-Triggered State Message Port Control Signal Port Safety- Memory Element Critical for a Single State Connector Message Unit Synchronized Clock Time-Triggered Communication Services of the TTA (see RTS lecture) 4

TTA Services of Interest • Synchronized real-time reference clock • Clock interrupt • Time-triggered network communication and I/O 5

Services we have to look at ... • Synchronized real-time clock reference • Clock interrupt • Time-triggered network communication and I/O • Operating system • Schedulability, scheduling • Task timing interferences • WCET assessment of single tasks 6

OS Software and Scheduling Remember: take control decisions offline!! Task model: simple tasks, single-path code Operating system structure & scheduling • Single-path code wherever possible • Static, table-driven scheduling: Offline decisions for I/O, comm., task switching and preemption • Use clock interrupt to synchronize with RT clock 7

Static Schedule Appl. tasks OS: clock int. handler OS: dispatching, c. switch T4 ... T1 T2’ T1 T2’’ T3 T1 Clock Interrupt OS: task switch Scheduled preemption Programmable clock interrupt Interrupt: start of defined task chains Statically scheduled preemptions à ??? Statically scheduled I/O and message access 8

Predictable Preemption??? Find a task preemption mechanism with fully predictable task preemption in presence of direct- mapped instruction caches We have to ensure that the HW & SW architecture guarantees convergence of cache behavior (prediction of cache behavior should be easy) 9

Variable Timing of Instruction Cache task 2 { … task 1 { … while (cond) { instr_k; instr_i; … } } … } multiple references to cache same code location conflict (e.g., stmts within loops, multiple calls of a function) 10

Clock-Driven Task Preemption System properties: • Actions of the system take place in a cyclic way • Tasks T i are periodic with periods p i • The duration of a scheduling round is defined as the least common multiple ( lcm ) of all task periods Straight-forward solution: è use a timer to trigger task preemption 11

Clock-Driven Task Preemption (2) I k Task trace T1 (higher priority) cache conflict Task trace T2 (lower priority) I i ’ I i same memory location 12

Clock-Driven Task Preemption (3) instruction timing I k Scenario A T1 cache miss penalty I i I i ’ T2 I k T1 I i I i ’ T2 Scenario B 13

Revised Strategy: Task Preemption by Instruction Count Task preemption within each scheduling round at statically determined instruction-count instances Realization: instruction-counter interrupt • hardware register to count the number of executed instructions (can be reset) • without HW support, code instrumentations raising a SW trap could serve the same purpose 14

Task Preemption by Instruction Counter First cycle T1 T2 T1 T2 All other cycles 15

Task Preemption by Instruction Counter Cache State: elements & position in cache Cache Content set of cache: elements in cache We need convergence of cache behavior! ➭ Stable Warmup of instruction cache: all future executions of a periodically executed fixed instruction sequence will show identical instruction hit/miss patterns. 16

Task Preemption by Instruction Counter Sufficient condition to reach Stable Warmup of instruction cache: 1. Hit/miss depends only on cache content set , not on cache state 2. On instruction access: element is placed at a well-defined position in cache (update of other elements is determined by their old position & current access) 3. Each element occurs at most once in the cache à Direct-Mapped Instruction Cache 17

Dealing with Clock Drift Master clock synchronization • Programmed clock interrupt from connector unit Planned variable-size window of inactivity before expected sync. time (needs bound on clock skew) window of inactivity slow CPU … fast CPU clock interrupt re-synchronization 18

Composability Temporal composability is not guaranteed in the presence of shared state (e.g., caches) A A B T2: T1: t 1 (A) t 2 (A) ? t 1 (A) = t 2 (A) Example: A and B in a loop; A fills the entire cache; ð cache conflicts between A and B 19

Prefetch Memory • Explicit load and store, planned offline • Consistent with pre-planning of schedules and pre-determined control flow of single-path code • Tool support to generate control code • Benefit from “knowledge of the future”: prefetching unit always knows the instructions that will be executed next à maximum number of hits 20

Prefetch Memory – Analysis 21

Prefetch Memory – Control Instr. ¡ DRAM PF Mem. Prefetch Controller Data ¡ CPU ¡ 22

A Time-Predictable Component Application Computer Symbols of a Component HRT Subsystem Time-Triggered State Message Port Control Signal Port Memory Element for a Single State Safety- Message Critical Connector Synchronized Clock Unit Time-Triggered Communication 23

Time-Predictable Component (2) synchronized representation of global time instruction counter “clock”, synchronized to the local representation of global time Static schedule (instruction-counter interrupt for preemptions) Data transfer triggered by progression of instruction counter clock Data transfer triggered by progression of global-time representation Programmable clock interrupt to synchronize the instruction- counter clock with the global-time representation 24

Conclusion We can construct a fully time-predictable node! You only have to observe two clocks and you will know the current action of the computer system: 1. CPU clock: controls all steps performed; ð count ticks to observe progress 2. Global-time interrupt: reference point synchronized with environment ð start counting ticks on the CPU clock when global-time interrupt occurs 25