Syed Aftab Rashid id, Geoffrey Nelissen and Eduardo Tovar 4/12/2016 - PowerPoint PPT Presentation

Syed Aftab Rashid id, Geoffrey Nelissen and Eduardo Tovar 4/12/2016

Main CPU Cache Memory Fast Slow 4/12/2016

Main CPU Cache Memory Fast Slow Limited capacity 4/12/2016

Main CPU Cache Memory Fast Slow Limited capacity Ƭ 1 Ƭ 2 4/12/2016

Main CPU Cache Memory Fast Slow Limited capacity Ƭ 1 Ƭ 2 4/12/2016

Main CPU Cache Memory Fast Slow Limited capacity Ƭ 1 Ƭ 2 Cache Related Preemption Delay (CRPD) 4/12/2016

• Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 Cache sets Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 Cache sets 5 4 3 2 1 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 Cache sets 5 4 3 2 1 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 9 8 Cache sets 7 6 5 5 4 4 3 2 1 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 9 8 Cache sets 7 6 5 5 4 4 3 2 1 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 9 8 Cache sets 7 6 5 5 5 4 4 4 3 3 2 2 1 1 0 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 9 9 8 8 Cache sets 7 7 6 6 5 5 5 5 4 4 4 4 3 3 2 2 1 1 0 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 9 9 8 8 Cache sets 7 7 6 6 5 5 5 5 5 4 4 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 600 700 9 9 9 8 8 8 Cache sets 7 7 7 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Cache Contents Fetched from Main CRPD Memory 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 600 700 9 9 9 8 8 8 Cache sets 7 7 7 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Cache Contents Fetched from Main CRPD Memory MD(R 2 )=MD 2 +3MD 1 +CRPD 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 600 700 9 9 9 8 8 8 Cache sets 7 7 7 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Cache Contents Fetched from Main CRPD Memory MD(R 2 )=MD 2 +3MD 1 +CRPD 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 600 700 9 9 9 9 8 8 8 8 Cache sets 7 7 7 7 6 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Cache Contents Fetched from Main CRPD Memory MD(R 2 )=MD 2 +3MD 1 +CRPD 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 600 700 9 9 9 9 9 8 8 8 8 8 Cache sets 7 7 7 7 7 6 6 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Cache Contents Fetched from Main CRPD Memory MD(R 2 )=MD 2 +3MD 1 +CRPD 4/12/2016

Ƭ 1 • Taskset { Ƭ 1, Ƭ 2 } C 1 = 100 and T 1 = 200 C 2 = 400 and T 2 = 1000 Ƭ 2 0 100 200 300 400 500 600 700 9 9 9 9 9 8 8 8 8 8 Cache sets 7 7 7 7 7 6 6 6 6 6 5 5 5 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Cache Contents Fetched from Main CRPD Memory MD(R 2 )=MD 2 +3MD 1 +CRPD MD(R 2 )=MD 2 +MD 1 +2(MD 1 – |PCB|) +CRPD 4/12/2016

4/12/2016

• Impr mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pree pr eempti mptive e systems ems 𝑆 𝑗 𝑢 = 𝑸 𝒋 + 𝑵𝑬 𝒋 + ෍ 𝑄 𝑘 + 𝑵𝑬 𝒌 + ෍ 𝑫𝑺𝑸𝑬 𝒋,𝒌 ∀𝑘 ∈ℎ𝑞 𝑗 ∀𝑘∈ℎ𝑞 𝑗 + ⌈𝑆 𝑗 𝑘 + 𝑵𝑬 𝒔 𝒌 + 𝑫𝑸𝑺𝑷 𝒌,𝒋 ) ෍ − 1⌉ ∗ (𝑄 𝑈 𝑘 ∀𝑘∈ℎ𝑞(𝑗) 4/12/2016

• Impr mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems 𝑆 𝑗 𝑢 = 𝑸 𝒋 + 𝑵𝑬 𝒋 + ෍ 𝑄 𝑘 + 𝑵𝑬 𝒌 + ෍ 𝑫𝑺𝑸𝑬 𝒋,𝒌 ∀𝑘 ∈ℎ𝑞 𝑗 ∀𝑘∈ℎ𝑞 𝑗 + ⌈𝑆 𝑗 𝑘 + 𝑵𝑬 𝒔 𝒌 + 𝑫𝑸𝑺𝑷 𝒌,𝒋 ) ෍ − 1⌉ ∗ (𝑄 𝑈 𝑘 ∀𝑘∈ℎ𝑞(𝑗) Considering the effect of PCBs 4/12/2016

• Impr mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems 𝑆 𝑗 𝑢 = 𝑸 𝒋 + 𝑵𝑬 𝒋 + ෍ 𝑄 𝑘 + 𝑵𝑬 𝒌 + ෍ 𝑫𝑺𝑸𝑬 𝒋,𝒌 ∀𝑘 ∈ℎ𝑞 𝑗 ∀𝑘∈ℎ𝑞 𝑗 Considering + evictions of PCBs ⌈𝑆 𝑗 𝑘 + 𝑵𝑬 𝒔 𝒌 + 𝑫𝑸𝑺𝑷 𝒌,𝒋 ) ෍ − 1⌉ ∗ (𝑄 𝑈 𝑘 ∀𝑘∈ℎ𝑞(𝑗) Considering the effect of PCBs 4/12/2016

• Impr mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems Considering the effect of CRPD 𝑆 𝑗 𝑢 = 𝑸 𝒋 + 𝑵𝑬 𝒋 + ෍ 𝑄 𝑘 + 𝑵𝑬 𝒌 + ෍ 𝑫𝑺𝑸𝑬 𝒋,𝒌 ∀𝑘 ∈ℎ𝑞 𝑗 ∀𝑘∈ℎ𝑞 𝑗 Considering + evictions of PCBs ⌈𝑆 𝑗 𝑘 + 𝑵𝑬 𝒔 𝒌 + 𝑫𝑸𝑺𝑷 𝒌,𝒋 ) ෍ − 1⌉ ∗ (𝑄 𝑈 𝑘 ∀𝑘∈ℎ𝑞(𝑗) Considering the effect of PCBs 4/12/2016

Proposed WCRT analysis State-of-the-art WCRT analysis 4/12/2016

• Extend the analysis to set et associ ociativ ative and data ta caches. • Provide a less pessimistic multi lti-se set t appr proa oach ch to calculate the impact of PCBs. • Combine approaches to calculate both th CRPD and impact of PCBs. • Extensi ensive e experim perimental ental evalua valuation tion using available benchmarks. 4/12/2016

4/12/2016