Syed Aftab Rashid id, Geoffrey Nelissen and Eduardo Tovar 4/12/2016 - - PowerPoint PPT Presentation

▶

Sep 05, 2023 267 likes •571 views

Syed Aftab Rashid id, Geoffrey Nelissen and Eduardo Tovar 4/12/2016 Main CPU Cache Memory Fast Slow 4/12/2016 Main CPU Cache Memory Fast Slow Limited capacity 4/12/2016 Main CPU Cache Memory Fast Slow Limited capacity 1

SLIDE 1

Syed Aftab Rashid id, Geoffrey Nelissen and Eduardo Tovar

4/12/2016

SLIDE 2

4/12/2016

CPU Cache Main Memory

Fast Slow

SLIDE 3

4/12/2016

CPU Cache Main Memory

Fast Slow Limited capacity

SLIDE 4

4/12/2016

CPU Cache Main Memory

Fast Slow Limited capacity Ƭ1 Ƭ2

SLIDE 5

4/12/2016

CPU Cache Main Memory

Fast Slow Limited capacity Ƭ1 Ƭ2

SLIDE 6

4/12/2016

CPU Cache Main Memory

Fast Slow Limited capacity Ƭ1 Ƭ2 Cache Related Preemption Delay (CRPD)

SLIDE 7

4/12/2016

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

SLIDE 8

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 Fetched from Main Memory CRPD

SLIDE 9

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 5 4 3 2 1 Fetched from Main Memory CRPD

SLIDE 10

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 5 4 3 2 1 Fetched from Main Memory CRPD

SLIDE 11

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 5 4 3 2 1 9 8 7 6 5 4 Fetched from Main Memory CRPD

SLIDE 12

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 5 4 3 2 1 9 8 7 6 5 4 Fetched from Main Memory CRPD

SLIDE 13

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

SLIDE 14

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 Fetched from Main Memory CRPD

SLIDE 15

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

SLIDE 16

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

9 8 7 6 5 4

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 600 700 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

SLIDE 17

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

9 8 7 6 5 4

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 600 700 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

MD(R2)=MD2+3MD1+CRPD

SLIDE 18

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

9 8 7 6 5 4

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 600 700 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

MD(R2)=MD2+3MD1+CRPD

SLIDE 19

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

9 8 7 6 5 4

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 600 700 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

MD(R2)=MD2+3MD1+CRPD

9 8 7 6

SLIDE 20

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

9 8 7 6 5 4

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 600 700 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

MD(R2)=MD2+3MD1+CRPD

9 8 7 6 9 8 7 6

SLIDE 21

4/12/2016

Ƭ1 Ƭ2

Cache Contents Cache sets

9 8 7 6 5 4

Taskset {Ƭ1, Ƭ2}

C1= 100 and T1= 200 C2= 400 and T2= 1000

100 200 300 400 500 600 700 5 4 3 2 1 9 8 7 6 5 4 3 2 1 5 4 9 8 7 6 5 4 3 2 1 5 4 3 2 1 5 4 Fetched from Main Memory CRPD

MD(R2)=MD2+3MD1+CRPD MD(R2)=MD2+MD1+2(MD1 –|PCB|) +CRPD

9 8 7 6 9 8 7 6

SLIDE 22

4/12/2016

SLIDE 23

4/12/2016

𝑆𝑗 𝑢 = 𝑸𝒋 + 𝑵𝑬𝒋 + ෍

∀𝑘 ∈ℎ𝑞 𝑗

𝑄

𝑘 + 𝑵𝑬𝒌 +

෍

∀𝑘∈ℎ𝑞 𝑗

𝑫𝑺𝑸𝑬𝒋,𝒌 + ෍

∀𝑘∈ℎ𝑞(𝑗)

⌈𝑆𝑗 𝑈

𝑘

− 1⌉ ∗ (𝑄

𝑘 + 𝑵𝑬𝒔𝒌 + 𝑫𝑸𝑺𝑷𝒌,𝒋)

Impr

mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems

SLIDE 24

4/12/2016

𝑆𝑗 𝑢 = 𝑸𝒋 + 𝑵𝑬𝒋 + ෍

∀𝑘 ∈ℎ𝑞 𝑗

𝑄

𝑘 + 𝑵𝑬𝒌 +

෍

∀𝑘∈ℎ𝑞 𝑗

𝑫𝑺𝑸𝑬𝒋,𝒌 + ෍

∀𝑘∈ℎ𝑞(𝑗)

⌈𝑆𝑗 𝑈

𝑘

− 1⌉ ∗ (𝑄

𝑘 + 𝑵𝑬𝒔𝒌 + 𝑫𝑸𝑺𝑷𝒌,𝒋)

Considering the effect of PCBs

Impr

mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems

SLIDE 25

4/12/2016

𝑆𝑗 𝑢 = 𝑸𝒋 + 𝑵𝑬𝒋 + ෍

∀𝑘 ∈ℎ𝑞 𝑗

𝑄

𝑘 + 𝑵𝑬𝒌 +

෍

∀𝑘∈ℎ𝑞 𝑗

𝑫𝑺𝑸𝑬𝒋,𝒌 + ෍

∀𝑘∈ℎ𝑞(𝑗)

⌈𝑆𝑗 𝑈

𝑘

− 1⌉ ∗ (𝑄

𝑘 + 𝑵𝑬𝒔𝒌 + 𝑫𝑸𝑺𝑷𝒌,𝒋)

Considering the effect of PCBs Considering evictions of PCBs

Impr

mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems

SLIDE 26

4/12/2016

𝑆𝑗 𝑢 = 𝑸𝒋 + 𝑵𝑬𝒋 + ෍

∀𝑘 ∈ℎ𝑞 𝑗

𝑄

𝑘 + 𝑵𝑬𝒌 +

෍

∀𝑘∈ℎ𝑞 𝑗

𝑫𝑺𝑸𝑬𝒋,𝒌 +

Considering the effect of CRPD

෍

∀𝑘∈ℎ𝑞(𝑗)

⌈𝑆𝑗 𝑈

𝑘

− 1⌉ ∗ (𝑄

𝑘 + 𝑵𝑬𝒔𝒌 + 𝑫𝑸𝑺𝑷𝒌,𝒋)

Considering the effect of PCBs Considering evictions of PCBs

Impr

mproved ed WCRT analysis is for r fix ixed ed pr prio iorit ity y pr pree eempti mptive e systems ems

SLIDE 27

4/12/2016

Proposed WCRT analysis State-of-the-art WCRT analysis

SLIDE 28

Extend the analysis to set

et associ

ciativ

ative and data ta caches.

Provide a less pessimistic multi

lti-se set t appr proa

ch to calculate the impact of PCBs.

Combine approaches to calculate both

th CRPD and impact of PCBs.

Extensi

ensive e experim perimental ental evalua valuation tion using available benchmarks.

4/12/2016

SLIDE 29

4/12/2016