Sub-lithographic Semiconductor Computing Systems Andr DeHon - - PowerPoint PPT Presentation

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Sub-lithographic Semiconductor Computing Systems Andr DeHon - - PowerPoint PPT Presentation

Aug 05, 2023 201 likes •729 views

Sub-lithographic Semiconductor Computing Systems Andr DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson, Charles Lieber, Patrick Lincoln, and John Savage MPSoC 2005 -- DeHon Approaching the Bottom In 1959,

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MPSoC 2005 -- DeHon

Sub-lithographic Semiconductor Computing Systems

André DeHon andre@cs.caltech.edu In collaboration with Helia Naeimi, Michael Wilson, Charles Lieber, Patrick Lincoln, and John Savage

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Approaching the Bottom

  • In 1959, Feynman pointed out we had

– “plenty of room at the bottom”

  • Suggested:

– wires ~ 10-100 atoms diameter – circuits ~ few thousands angstroms ~ few hundred nm

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Approaching the Bottom

  • Today we have 90nm Si processes

– bottom is not so far away

  • Si Atom

– 0.5nm lattice spacing – 90nm ~ 180 atoms diameter wire

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Exciting Advances in Science

  • Beginning to be able to manipulate

things at the “bottom” -- atomic scale engineering

– designer/synthetic molecules – carbon nanotubes – silicon nanowires – self-assembled mono layers – designer DNA

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Question

  • Can we build interesting computing

systems using these bottom-up building blocks?

– without using lithographic patterning for our smallest feature sizes?

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Focus Challenge

  • How build programmable logic

from nanowires and molecular- scale switches?

–With regular self-assembly –With high defect rates

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Today’s Talk

Bottom up tour: from Si atoms to Computing

  • Nanowire Building Blocks

– growth – devices – assembly – differentiation – coding

  • Logic: nanoPLAs
  • Analysis
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SiNW Growth

  • Self-same crystal

structure constrains growth

  • Catalyst

defines/constrains structure

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SiNW Growth

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SiNW Growth

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Building Blocks

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Semiconducting Nanowires

  • Few nm’s in diameter (e.g. 3nm)

– Diameter controlled by seed catalyst

  • Can be microns long
  • Control electrical properties via doping

– Materials in environment during growth – Control thresholds for conduction

From: Cui…Lieber APL v78n15p2214

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Radial Modulation Doping

  • Can also control doping profile radially

– To atomic precision – Using time

Lauhon et. al. Nature 420 p57

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Devices

Diode and FET Junctions

Doped nanowires give:

Huang…Lieber Science 294 p1313 Cui…Lieber Science 291 p851

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Langmuir-Blodgett (LB) transfer

  • Align Nanowires
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Langmuir-Blodgett (LB) transfer

  • Can transfer tight-packed, aligned SiNWs
  • nto surface

– Maybe grow sacrificial outer radius, close pack, and etch away to control spacing +

Transfer aligned NWs to patterned substrate Transfer second layer at right angle

Whang, Nano Letters 2003 v7n3p951

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Homogeneous Crossbar

  • Gives us homogeneous NW crossbar

– Undifferentiated wires – All do the same thing

  • Can we build arbitrary

logic starting with regular assembly?

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Control NW Dopant

  • Can define a dopant profile along

the length of a wire

– Control lengths by timed growth – Change impurities present in the environment as a function of time

Gudiksen et al. Nature 415 p617 Björk et al. Nanoletters 2 p87

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Control NW Dopant

  • Can define a dopant profile along

the length of a wire

– Control lengths by timed growth – Change impurities present in the environment as a function of time

  • Get a SiNW banded with

differentiated conduction/gate-able regions

Gudskien et. al. Nature 415 p617 Björk et. al. Nanoletters 2 p87

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Enables: Differentiated Wires

  • Can engineer wires

– Portions of wire always conduct – Portions controllable

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Switches / Memories

Molecular Switches

Collier et al. Science 289 p1172

Electrostatic Switches

Ruekes et al. Science 289 p04

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Common Switchpoint Properties

  • Fit in space of NW crossing
  • Hysteretic I-V curves
  • Set/reset with large differential voltage

across crosspoint

  • Operate at lower voltage
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…on to Logic…

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Diode Logic

  • Arise directly from

touching NW/NTs

  • Passive logic
  • Non-restoring
  • Non-volatile

Programmable crosspoints

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Use to build Programmable OR-plane

  • But..

– OR is not universal – Diode logic is non-restoring no gain, cannot cascade

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PMOS-like Restoring FET Logic

  • Use FET

connections to build restoring gates

  • Static load

– Like NMOS (PMOS)

  • Maybe precharge
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Operating Point: Make Restoring

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Restoration Array

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Simple Nanowire-Based PLA

NOR-NOR = AND-OR PLA Logic FPGA 2004

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Defect Tolerant

All components (PLA, routing, memory) interchangeable; Have M-choose-N property Allows local programming around faults

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Crosspoint Defects

  • Crosspoint junctions may be

nonprogrammable

– E.g. HPs first 8x8 had 85% programmable crosspoints

  • Tolerate by matching

nanowire junction programmability with pterm needs

Design and Test of Computers, July-August 2005 Naeimi/DeHon, FPT2004

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Simple PLA Area

  • 60 OR-term PLA

– Useable

  • 131 raw row

wires

– Defects – Misalign

  • 171 raw

inverting wires

– Defects – Statistical population

  • 60M sq. nm.

– (2 planes) 90nm support lithography; 10nm nanowire pitch

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Scaling Up

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Scaling Up

  • Large arrays are not viable

–Not exploit structure of logic –Long Nanowires tend to break –Long Nanowires will be slow

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Interconnect nanoPLA Arrays

FPGA 2005

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Interconnect nanoPLA Arrays

FPGA 2005

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Interconnected nanoPLA Arrays

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Interconnected nanoPLA Arrays

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Complete Substrate for Computing

  • Know NOR gates are

universal

  • Selective inversion
  • Interconnect structure for

arbitrary routing Can compute any logic function

  • Can combine with

nanomemories

  • Programmable

structure similar to today’s FPGAs

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Interconnected nanoPLA Tile

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Analysis

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Area Mapped Logic

  • Take standard CAD/Benchmark designs

– Toronto20 used for FPGA evaluation

  • Map to PLAs
  • Place and Route on arrays of various

configurations

  • Pick Best mapping to minimize Area
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Mapped Logic Density (105/10/5)

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Nanowire Lengths: 105/10/5/Ideal Restore/Pc=0.95

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Cycle Delay: 105/10/5/Ideal Restore/Pc=0.95

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Construction

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Manufacturing Flow

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Manufacturing Flow

  • Stochastic differentiation of Nanowires
  • Post-fabrication configuration to define

function and avoid defects

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Power Density (per GHz)

  • Vdd=1V
  • Active Power
  • Precharge
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Summary

  • Can engineer designer structures at atomic scale
  • Must build regular structure

– Amenable to self-assembly

  • Can differentiate

– Stochastically – Post-fabrication programming

  • Sufficient building blocks to define universal

computing systems without lithography

  • Reach or exceed extreme DSM lithography

densities

– With modest lithographic support

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Additional Information

  • <http://www.cs.caltech.edu/research/ic/>
  • <http://www.cmliris.harvard.edu/>